Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2005-07-20
2008-09-23
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S600000
Reexamination Certificate
active
07428653
ABSTRACT:
An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within a single clock cycle. Thus, each thread is executed once per clock cycle and two threads are executed in a single clock cycle.
REFERENCES:
patent: 5694604 (1997-12-01), Reiffin
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 7000233 (2006-02-01), Levitan et al.
Bindloss Keith
Budrovic Marty T.
Fisher Duncan M.
Gupta Rajiv
Su Ching Long
Mindspeed Technologies Inc.
Perveen Rehana
Rahman Michael A.
Rehman Mohammed H
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