Method and system for error detection in test units utilizing ps

Details Method and system for error detection in test units utilizing ps Method and system for error detection in test units utilizing ps

1998-02-25

2000-10-17

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714728, G01R 3128

Patent

active

061346845

ABSTRACT:
A method and system in an integrated circuit for the detection of defects within integrated circuits and planars are disclosed. Initially, pseudo-random data is generated. Thereafter, the pseudo-random data is transferred to a bus interface unit that determines, based upon the pseudo-random data, a particular transaction that may be injected upon a test unit by the bus interface unit. Expected results of all types of transactions that may be injected upon the test unit are predetermined. The particular transaction is then injected upon the test unit. Such transactions can include transactions such as a bus store or bus load. The results of the particular transaction upon the test unit are then compared with the expected results, wherein a mismatch between the expected results and the results of the particular transaction upon the test unit exposes an error within the test unit, such that a variety of test units may be portably tested for errors without the need for preconfiguring the test units for testing.

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