Method and system for efficiently fetching from cache during a c

Details Method and system for efficiently fetching from cache during a c Method and system for efficiently fetching from cache during a c

1997-06-24

1999-04-27

Treat, William M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711149, 711133, 711168, G06F 1300

Patent

active

058976540

ABSTRACT:
A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.

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