Method and system for displaying VLSI layout data

Details Method and system for displaying VLSI layout data Method and system for displaying VLSI layout data

2005-04-26

2005-04-26

Tran, M. (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06886148

ABSTRACT:
A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them to be displayed efficiently and accurately independent of the canonical expression of the VLSI design. The VLSI layout editor and methods for using same use precomputed images that each represent a portion of the VLSI layout, a hierarchy cache that includes multiple LOD versions of selected sub-designs in the pre-computed images, and selected direct determination of the viewable representation from the canonical expression for at least one LOD. Apparatus and methods according to the present invention can render a particular type of data whose canonical form is smaller than its corresponding displayed image thereof when the displayed image has geometric properties that allow heuristics and rasterization for dynamic and accurate expansion using selected combined techniques. Texture mapping and mipmapping can be used to accurately reduce, expand and reorder layers in a viewable image expanded from a canonical expression of the VLSI layout.

REFERENCES:
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patent: 5481717 (1996-01-01), Gaboury
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IC Station Stream View by Mentor Graphics Product Description Data Sheet, 2 pp.
Virtuoso Layout Editor by Cadence Design Systems, Inc. Product Description Data Sheet, 3 pp.

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