Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-29
2005-11-29
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S732000
Reexamination Certificate
active
06971054
ABSTRACT:
An exemplary embodiment of the present invention is a method for testing an integrated circuit. The method includes generating a test pattern and generating a reference signature corresponding to the test pattern. An integrated circuit test is executed in response to the test pattern and a result signature is generated in response to data output from executing the integrated circuit test. The result signature is compared to the reference signature and a current failing signature is created if the two don't match. The current failing signature is copy of the result signature. Common error analysis is executed in response to creating the current failing signature. Additional embodiments include a system and storage medium for testing an integrated circuit.
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Kurtulik Raymond J.
Motika Franco
Rizzolo Richard F.
Augspurger Lynn
Britt Cynthia
Cantor & Colburn LLP
De'cady Albert
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