Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-02-22
2003-04-29
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S732000
Reexamination Certificate
active
06557132
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the testing of semiconductor integrated circuit devices and, more particularly, to an improved method and system for determining common failure modes for test data applied to an integrated circuit device under test.
Complex very large scale integrated circuit (VLSI) devices fabricated upon a single semiconductor chip contain thousands of functional circuit elements which are generally inaccessible for testing purposes. Because of the complexity of the internal connections and their combinational interdependencies, testing of such devices becomes increasingly cumbersome as the number of circuit elements increases. For example, a semiconductor chip with 50 input terminals has 2
50
possible digital input combinations. Thus, applying that many input patterns during testing and then comparing the resulting output responses to a set of expected outputs is a task too cumbersome for modern production testing.
Consequently, a known testing protocol involves the generation of pseudo-random patterns or test vectors to considerably reduce the number of test patterns required to test a circuit. In Weighted Random Pattern (WRP) generation, differently configured sequences of random patterns are applied in parallel to each input terminal of a Device Under Test (DUT). The output responses of the patterns are then collected from each output in parallel and then combined so as to obtain a “signature function” of all the sequences of parallel outputs. These test signatures are then compared with corresponding known “good” signatures obtained by computer simulation, thereby obviating the need to compare each individual test response to a known good output response.
In addition to reducing testing time, it is also desirable to ascertain the specific failure mode of a device. Common failure modes (as opposed to random failures), are generally symptomatic of conditions such as manufacturing process problems or design defects. Accordingly, discovering and eliminating common failure modes is important in improving device yield. Thus, when reviewing the signatures of failed vectors, it is desirable to know whether a recognizable pattern of signatures exists, thereby indicting a common failure mode or modes.
In order to detect repeating vector fails from one device to the next, previous testing methods have captured the failing vector states and locations and compared the same to find similarities. However, such a technique necessarily uses some implementation of pattern recognition function. Moreover, the collection of failed vector data typically takes a considerable amount of time. Not only are multiple testing resources accessed during this process, but the fail capturing mechanism of most testing devices is orders of magnitude smaller than the testing vector resources. As a result, the multiple execution of patterns is required to collect all of the failing vectors.
SUMMARY OF THE INVENTION
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for determining common failure modes of an integrated circuit device under test. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.
In a preferred embodiment, the output signature is stored if the output signature does not match a previously stored output signature. An indication signal is also generated if the fail data corresponding to the output signature has been stored. Preferably, the output signature is created by a series of single input shift registers connected to a series of outputs of the device under test.
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Gangl David V.
Grady Matthew Sean
Iverson David John
Lavallee Kenneth A.
Shearer Robert Edward
Cantor & Colburn LLP
International Business Machines - Corporation
Tu Christine T.
Walsh Robert A.
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