Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-06-30
2001-01-23
Tu, Trinh L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000, C714S032000
Reexamination Certificate
active
06178533
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
The present invention relates generally to systems and methods for design verification of electronic circuits. More particularly, the invention relates to pseudo-random testing of electronic circuits that may be used in computers or other processing machines.
BACKGROUND OF THE INVENTION
During the development and manufacture of electronic circuits, there is a need to vigorously test various designs and products before release to customers. Ideally, the performance of an electronic circuit, for example a microprocessor, is verified for all possible circumstances under which it might be operated in the real world. Unfortunately, this would involve exhaustively testing a potentially infinite number of machine operation sequences and therefore require a prohibitively long time to generate and run test sequences.
To sample a wide range of possible machine operation sequences for design verification, random instruction generators were developed. These systems simply generate a random sampling of instructions (typically in the microprocessor's assembly language) which is then converted to machine code and tested on the microprocessor. Typically the instructions that are tested are limited to those instructions that test the functionality of the microprocessor's internal units.
However, these generators suffer from several limitations. Although such systems can provide a wide range of possible microprocessor operations with minimal user input, they have no understanding of what operation sequences are likely to be encountered in the real world. Further, they do not understand which operation sequences might be most difficult for the microprocessor to handle. Thus, they sometimes fail to adequately test important aspects of a microprocessor's functioning.
Another limitation is that the functionality of the microprocessor in executing externally-generated requests cannot be tested. The current trend is for microprocessors to include a bus interface unit to handle data requests from devices connected to the microprocessor's external bus. The random instruction generators normally do not generate instructions to test the microprocessor's behavior in responding to these external devices.
Accordingly, there exists a need for a test verification system that can overcome these shortcomings.
SUMMARY OF THE INVENTION
The present invention pertains to a dynamic process for generating biased pseudo-random test patterns for the functional verification of integrated circuit designs. In a preferred embodiment of the present invention, test patterns are generated to verify the functionality of a microprocessor having a bus interface unit that is capable of direct memory access (DMA) operations between I/O devices attached to an external bus and the microprocessor's memory. The test patterns can verify the microprocessor's functionality, particularly the memory operations performed by the microprocessor and DMA operations performed by the microprocessor's bus interface unit. These test patterns can then be used by a simulation mechanism to simulate the expected results of the target microprocessor design executing the generated sequence of transactions.
Two sets of test patterns are generated by the test verification system. The first set of test patterns are assembly code instructions written in the microprocessor's instruction set which test memory operations initiated by control units located within the microprocessor. In addition, the first set of test patterns include memory initialization and memory mapping instructions. The second set of test patterns are instructions that test DMA operations initiated from external I/O devices connected to the microprocessor.
The test verification system categorizes the verifiable operations into transactions. Each transaction consists of one or more instructions. Each transaction is assigned a user-defined weight that is used to bias the frequency that a transaction type is tested. The test verification system selects a particular transaction category based on the user-defined weights and generates the corresponding instructions or test patterns that implement the transaction.
The present invention is beneficial for several reasons. First, it is capable of verifying DMA operations initiated from external I/O devices connected to the microprocessor. Further, it provides the user with the capability of selecting those transactions that are to be tested more frequently than others by utilizing user defined weight factors.
REFERENCES:
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5572666 (1996-11-01), Whitman
patent: 5729554 (1998-03-01), Weir et al.
Pennie & Edmonds LLP
Sun Microsystems Inc.
Tu Trinh L.
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