Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-08
2008-07-08
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S011000, C714S021000, C714S025000, C714S037000, C714S045000, C714S724000, C714S729000, C714S734000, C703S013000, C703S015000, C703S019000, C703S022000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07398445
ABSTRACT:
A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified.
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Larouche Mario
Ng Chun Kit
Blakely , Sokoloff, Taylor & Zafman LLP
Synplicity, Inc.
Trimmings John P
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