Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2009-06-19
2011-12-13
Doan, Nghia (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S050000, C716S051000, C716S054000, C716S055000, C430S005000, C430S030000, C355S402000, C355S403000
Reexamination Certificate
active
08078996
ABSTRACT:
A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
REFERENCES:
patent: 5879844 (1999-03-01), Yamamoto et al.
patent: 5969801 (1999-10-01), Tsudaka
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6221539 (2001-04-01), Kotani et al.
patent: 6470489 (2002-10-01), Chang et al.
patent: 6665856 (2003-12-01), Pierrat et al.
patent: 7384710 (2008-06-01), Ogawa et al.
patent: 7571417 (2009-08-01), Izuha et al.
patent: 09-319067 (1997-12-01), None
patent: 2003-167323 (2003-06-01), None
patent: 2003-303742 (2003-10-01), None
Notification of Reasons for Rejection issued by the Japanese Patent Office on Apr. 1, 2008, for Japanese Patent Application No. 2003-421349, and English-language translation thereof, (see U.S. Appl. No. 11/012,494).
Newmark, D. M. et al., “Large Area Optical Proximity Correction Using Pattern Based Corrections”, SPIE, vol. 2322, Photomask Technology and Management, pp. 374-386, (1994), (see U.S. Appl. No. 11/012, 494).
Izuha Kyoko
Kotani Toshiya
Nojima Shigeki
Tanaka Satoshi
Doan Nghia
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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