Method and system for coding test pattern for scan design

Details Method and system for coding test pattern for scan design Method and system for coding test pattern for scan design

2007-05-29

2007-05-29

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000, C714S726000, C714S733000, C714S724000, C716S030000

Reexamination Certificate

active

10630957

ABSTRACT:
A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.

REFERENCES:
patent: 5991909 (1999-11-01), Rajski et al.
patent: 6029261 (2000-02-01), Hartmann
patent: 2003/0149913 (2003-08-01), Balachandran et al.
“LFSR-Coded Test Patterns for Scan Designs” by B. Konemann, pp. 237-242.
“Decompression of Test Data Using Variable-Length Seed LFSRs” by J. Rajski et al, 1995 IEEE, pp. 426-433.

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