Method and system for automated path delay test vector...

Details Method and system for automated path delay test vector... Method and system for automated path delay test vector...

2006-09-22

2009-12-29

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07640476

ABSTRACT:
Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit design. The system and methods can systematically and automatically perform functional and structural testing on selected paths of the circuit design and, in turn, generate one or more test vectors to increase PDT test coverage using the results of the structural test on the selected path.

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patent: 2005/0240887 (2005-10-01), Rajski et al.
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