Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-12-24
2001-06-05
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C712S207000, C711S213000
Reexamination Certificate
active
06243822
ABSTRACT:
BACKGROUND OF THE INVENTION
Off-chip memory access is, for the most part, significantly slower than CPU instruction execution. Data access from off-chip memory therefore acts as a bottleneck that decreases the speed at which the processor can execute programs. This is especially true when an entire array of data must be loaded from memory into registers.
SUMMARY OF THE INVENTION
The present invention decreases the delay associated with loading an array from memory by employing an asynchronous array preload unit. The asynchronous array preload unit provides continuous preliminary loading of data arrays located in a memory subsystem into a prefetch buffer. Array loading is performed asynchronously with respect to execution of the main program.
A preferred embodiment of the present invention comprises a loop program having two parts: an asynchronous part (“asynchronous program”) and a synchronous part. The synchronous part of the loop program is part of the main program executed by the system. The asynchronous program performs preliminary loading of array elements from the memory subsystem into a special buffer. Execution of the asynchronous program is started by the main program which times the start of the asynchronous program so that before execution of the synchronous part of the loop program, the necessary array data are already in the prefetch buffer. The asynchronous part of the program works asynchronously and simultaneously with the main program execution.
The synchronous part of the loop program transfers array elements from the buffer to the register file and performs other necessary operations over array elements.
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HPL Play-Doh Architecture Specification: Version 1.0 Vinod Kathail, Michael Schlansker, B. Ramakrishna Rau, Computer Systems Lab, HPL-93-80 Feb. 1994.
Babaian Boris A.
Chudakov Mikhail L.
Konopleff Oleg A.
Sakhin Yuli K.
Vechtomov Andrey A.
Butler Dennis M.
Elbrus International Limited
Townsend and Townsend and Crew
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