Method and system for an efficient user mode cache manipulation

Details Method and system for an efficient user mode cache manipulation Method and system for an efficient user mode cache manipulation

1996-09-06

2000-04-11

Lall, Parshotam S.

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

711123, 711141, 711154, G06F 1208

Patent

active

060498668

ABSTRACT:
A method and a system for fast user mode cache synchronization. The present invention is implemented on a computer system having a instruction cache. The system of the present invention detects a simulated instruction from a process running on the computer system while the process is running in a user mode. The simulated instruction causes an error exception and the operating system traps the error. The kernel then interprets the simulated instruction is then as an instruction cache synchronization instruction. The instruction cache synchronization instruction is executed and the program counter is incremented. The present invention then returns to the process in user mode. During instruction execution, preloaded registers that contain a starting address and an ending address, defining an address range, are read. The entries of the instruction cache are read and those entries falling within the address range are marked as invalid to maintain instruction cache coherency.

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Motorola (M6800) "8-/16-/32-Bit Microprocessors Programmer's Refernce Manual" fifth edition p. 4-10 to 4-11, 1986.
Motorola (MC68030) "Enhanced 32-Bit microprocessor user's manual second edition", 1989.
(Alpha Architecture Reference Manual) Sites; Digital Press p. 4-115, Jul. 1992.

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