Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-11-20
2007-11-20
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S154000
Reexamination Certificate
active
11147791
ABSTRACT:
A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical “0” and logical “1”. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.
REFERENCES:
patent: 5255230 (1993-10-01), Chan et al.
patent: 5717645 (1998-02-01), Kengeri et al.
patent: 5808959 (1998-09-01), Kengeri et al.
patent: 6259634 (2001-07-01), Kengeri et al.
patent: 6434040 (2002-08-01), Kim et al.
patent: 6452834 (2002-09-01), Kengeri
patent: 6501692 (2002-12-01), Melanson et al.
patent: 6643804 (2003-11-01), Aipperspach et al.
patent: 6667917 (2003-12-01), Templeton et al.
patent: 6711076 (2004-03-01), Braceras
patent: 6788574 (2004-09-01), Han et al.
patent: 6992938 (2006-01-01), Shubat et al.
patent: 7069522 (2006-06-01), Sluss et al.
patent: 7130213 (2006-10-01), Raszka
patent: 7149924 (2006-12-01), Zorian et al.
patent: 2006/0187724 (2006-08-01), Pineda De Gyvez et al.
Josh Yang et al., “Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode”, IEEE Computer Society, Proceedings of the 7thInternational Conference on VLSI Design (VLSID'04), 2004 IEEE, pp. 6 total.
Doe-Hyun Yoon et al., “Dynamic Power Supply Current Testing for Open Defects in CMOS SRAMs”, ETRI Journal, vol. 23, No. 2, Jun. 2001, pp. 77-84.
Bhatia Prakash
Kainth Sanjiv
Kengeri Subramani
Sabharwal Deepak
Blakely , Sokoloff, Taylor & Zafman LLP
Phung Anh
Virage Logic Corporation
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