Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-05-06
2008-05-06
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S111000, C711S118000, C365S049130, C714S002000, C714S005110, C714S041000, C714S042000
Reexamination Certificate
active
10690137
ABSTRACT:
A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.
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Asher David H.
Fitzgerald Patrick M.
Grodstein Joel
Lilly Brian
Elmore Stephen C.
Hewlett--Packard Development Company, L.P.
Kim Daniel
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