Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-28
2002-08-13
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S132000, C438S281000, C438S333000, C438S467000, C438S601000, C257S529000
Reexamination Certificate
active
06432760
ABSTRACT:
DESCRIPTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to programming electrical fuses in integrated circuit (IC) devices and, more particularly, to an improved method and structure to reduce the damage associated with programming electrical fuses.
2. Background Description
Fuses are fabricated on various IC devices, such as memory arrays, to improve the yield during manufacturing. They are also used in some devices, such as field programmable arrays (FPGAs), to allow customization of the IC device for a particular application. Commonly, fuse structures are realized by patterning a gate stack (polysilicon and cobalt/tungsten silicide) to the appropriate dimensions. An etch-stop silicon nitride layer is deposited over the silicide as part of the fabrication process. The fusing process passes an electrical current through the fuse element to melt the fuse link by the resistive heating of the element. The location of the breakage is dependent on the defect structure in the fuse link.
Significant energy is needed to blow the fuse manufactured according to the current process. This leads to the generation of cracks in the surrounding layers. To prevent damage to other structures, the fuses are often laid out in a guarded area.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved fuse structure which does away with the need to isolate the fuse structure to prevent damage to other structures.
It is another object of the invention to provide a fuse structure which exhibits improved reliability, efficiency, yield and packing density.
According to the invention, there is provided a new fuse structure which replaces the brittle and relatively inert nitride and silicon dioxide layer in current fuses with a soft passivation layer. The inherent ductility present in the soft passivation layer prevents the generation of cracks. In addition, this reduces pressure on the silicide link, allowing it to melt easily, lowering the current required to blow the fuse.
Specifically, during the manufacture of the fuse structure, the brittle and relatively inert silicon nitride and silicon dioxide layer is removed and a soft passivation layer is applied. A preferred material for the soft passivation layer is known in the art as “SILK” for Silicon Low K. Other possible materials could be various “spin-on” dielectrics such as fluorosilicate glass or siloxane containing polymers.
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patent: 5970346 (1999-10-01), Liaw
patent: 6124165 (2000-09-01), Lien
patent: 6271574 (2001-08-01), Delpech et al.
patent: 6300252 (2001-10-01), Ying et al.
patent: 6372652 (2002-04-01), Verma et al.
Iyer Sundar K.
Kothandaraman Chandrasekharan
Stetter Michael
Braden Stanton
Infineon - Technologies AG
Kang Donghee
Thomas Tom
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