Method and structure to improve the gate coupling ratio...

Details Method and structure to improve the gate coupling ratio... Method and structure to improve the gate coupling ratio...

2005-05-24

2005-05-24

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S596000

Reexamination Certificate

active

06897116

ABSTRACT:
Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device are provided. The method and structure include the following steps. A gate oxide layer, a first semiconductor layer, and an insulating layer are formed sequentially over a provided semiconductor substrate. An etching process is used to etch the insulating layer. A semiconductor spacer is then deposited and used as a self-aligned etching mask. After the self-aligned etching, the insulating layer is removed and an insulating stacked structure is deposited. Finally, a second semiconductor layer is deposited and etched to form the control gate region.

REFERENCES:
patent: 6171909 (2001-01-01), Ding et al.
patent: 6172394 (2001-01-01), Nakagawa
patent: 6403421 (2002-06-01), Ikeda et al.
patent: 6562681 (2003-05-01), Tuan et al.

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