Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-31
2006-10-31
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S243000, C438S253000, C438S386000, C438S387000, C438S396000, C257S077000, C257S296000, C257S301000, C257S303000, C257S306000, C257S310000, C257S532000
Reexamination Certificate
active
07129133
ABSTRACT:
Disclosed are methods and structures for fabrication of reliable and efficient memory cells. The methods involve formation of a conformal diffusion barrier layer in a via, deposition of an electrode material in the via, removal of a certain portion of the electrode material from the via to expose a the portion of the diffusion barrier layer, converting the exposed portion of the diffusion barrier layer into an oxide, forming a memory element film, and forming and patterning a top electrode. Improved electrical conduction and data retention from the memory element of a memory cell by preventing short circuits and leakage of current through the conductive diffusion barrier layer, and thereby enhanced reliability and performance of a memory cell are obtained.
REFERENCES:
patent: 6281142 (2001-08-01), Basceri et al.
patent: 6344413 (2002-02-01), Zurcher et al.
patent: 6656763 (2003-12-01), Oglesby et al.
patent: 6686263 (2004-02-01), Lopatin et al.
patent: 6746971 (2004-06-01), Ngo et al.
patent: 6753247 (2004-06-01), Okoroanyanwu et al.
patent: 6768157 (2004-07-01), Krieger et al.
patent: 6770905 (2004-08-01), Buynoski et al.
patent: 6773954 (2004-08-01), Subramanian et al.
patent: 6781868 (2004-08-01), Bulovic et al.
patent: 6787458 (2004-09-01), Tripsas et al.
patent: 6940112 (2005-09-01), Rhodes et al.
patent: 2003/0025142 (2003-02-01), Rhodes et al.
patent: 2004/0053465 (2004-03-01), Hong
patent: 2005/0003609 (2005-01-01), Fazan et al.
Avanzino Steven C.
Tran Minh
Amin & Turocy LLP
Fourson George
Garcia Joannie Adelle
Spansion LLC
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