Method and structure of an auxiliary transistor arrangement...

Details Method and structure of an auxiliary transistor arrangement... Method and structure of an auxiliary transistor arrangement...

2006-09-26

2006-09-26

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07112496

ABSTRACT:
Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.

REFERENCES:
patent: 4424526 (1984-01-01), Dennard et al.
patent: 6521487 (2003-02-01), Chen et al.
patent: 2002/0185662 (2002-12-01), Watatani
patent: 3931381 (1991-03-01), None

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