Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2000-06-02
2003-05-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S020000, C257S024000, C257S027000, C257S066000, C257S353000, C257S347000
Reexamination Certificate
active
06563131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to structures and manufacturing methods for integrated circuits including field effect transistors (FETs) and, more particularly to high performance FETs suitable for integrated circuits formed at high integration density.
2. Description of the Prior Art
It has been recognized for some years that increased integration density in integrated circuits provides not only improvements in performance and functionality but manufacturing economy, as well. Reduced device sizes and increased numbers of devices on a single chip of a given size have required designs operable at reduced voltages to accommodate both breakdown voltages of smaller and thinner structures and total chip heat dissipation as higher clock frequencies are employed in greater numbers of devices. Unfortunately, as devices are scaled to smaller sizes and operated at lower voltages, some electrical effects are encountered which are deleterious to device performance.
Specifically, one effect of reducing channel or gate length below 50 nanometers (and reduction of operating voltage) is the finite depth in the FET channel which can be controlled by the gate. If conduction cannot be controlled over the full depth of the conduction channel, so-called off-current is increased, reducing operating margins already limited by reduced voltage operation and increasing noise susceptibility of the circuits integrated on the chip. Power dissipation is also increased since the transistors, in effect, cannot be fully turned off.
It is known to place gates on opposing sides of a channel of an FET (essentially variations on substrate bias of very early FETs) and theoretical and experimental studies have confirmed that substantial improvements in FET performance are possible using gate structures which partially or fully surround the conduction channel. However, these same studies have demonstrated a requirement for an extremely thin diffusion region since, for short gate lengths of interest, the gate length must be maintained about 2-4 times the diffusion thickness.
That is, for gate lengths of 20-100 nanometers, the diffusion thickness forming the channel must be held to 5-50 nanometers. Such a thin diffusion region has not been possible consistent with other process requirements of FETs even where the gate does not partially surround the channel. Therefore, this effect encountered at short gate lengths clearly imposes a trade-off between performance and minimum transistor dimensions and thus presents a severe limitation on device size and integration density.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a field effect transistor structure with a particularly short gate length while providing good performance, including low off-current.
It is another object of the invention to provide a practical manufacturing method, consistent with high integration density, for FETs having reduced gate length.
In order to accomplish these and other objects of the invention, a field effect transistor and an integrated circuit are provided comprising a conduction channel, and a gate located on at least two sides of said conduction channel and separated from a source region. The separation of the gate from the source reduces gate-source capacitance and allows epitaxial growth of the channel from the transistor source region to also form the transistor drain.
In accordance with another aspect of the invention a method of fabricating an integrated circuit including a field effect transistor having a conduction channel and a gate located on at least two sides of the conduction channel and separated from a source region, is provided comprising steps of patterning a doped silicon layer to form separated gate and source structures, forming a trough in the gate and source structures, forming an oxide film in the trough in the gate structure, and epitaxially growing a conduction channel and a drain region from the source structure through the gate structure.
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Adkisson James W.
Agnello Paul D.
Ballantine Arne W.
Putnam Christopher S.
Rankin Jed H.
Calderon Andrew M.
Chadurjian Mark F.
International Business Machines - Corporation
Lee Eddie
Nguyen Joseph
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