Method and structure for vertical DRAM devices with...

Details Method and structure for vertical DRAM devices with... Method and structure for vertical DRAM devices with...

2005-07-05

2005-07-05

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S257000

Reexamination Certificate

active

06913968

ABSTRACT:
A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.

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S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, Lattice Press, California, pp. 307-308, 323-324.

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