Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-01
2003-12-16
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S386000
Reexamination Certificate
active
06664161
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor processing method, and more particularly to a method and structure for forming an electrode within a trench capacitor in a semiconductor substrate.
BACKGROUND OF THE INVENTION
A DRAM or a dynamic random access memory has a plurality of memory cells formed in a matrix manner on a substrate. Each memory cell typically includes a single transfer gate transistor coupled to a single capacitor. Three dimensionally configured capacitors have been developed and used for these memory cells to realize a higher degree of integration. The three dimensionally configured capacitors may be either of a stacked structure or of a trench structure. The trench structure is advantageous to the stacked structure in situations where the surface flatness of the device is of great importance. In this type of semiconductor memory, an opening is etched in a semiconductor substrate, and a storage capacitor is formed in the opening.
Storage capacitors require a plate electrode for maintaining a fixed reference potential, against which a value is stored in the memory cell as a variable potential on a node electrode, which is separated from the plate electrode by a node dielectric. When the plate electrode is formed on the outer wall of a trench capacitor beneath the upper surface of the semiconductor substrate, it is known as a buried plate.
An existing method of making the buried plate of a trench capacitor is by gas-phase doping of arsenic into the semiconductor sidewalls of the lower portion of the trench to form a buried plate outdiffusion. This creates a depletion region in the substrate region surrounding the trench. The depletion region, having a capacitance in series with the capacitance across the node dielectric, leads to a lower overall node capacitance. If depletion capacitance is eliminated, the improved node capacitance would help promote increased integration density by permitting smaller trenches to be used.
Moreover, gas-phase doping of arsenic to form the buried plate requires use of a compatible node electrode material, such as polysilicon, such that no workfunction difference exists between the node and plate electrode materials. In such way, the back bias on the plate electrode can be maintained at a level halfway (e.g. 0.75 V) between the low (0 V) and high (1.5V) node potentials, which is most desirable for signal margins and avoiding leakage current off the capacitor.
However, the resistivity of the node electrode is becoming a considerable factor in the switching speeds that are needed today. Polysilicon, though highly doped to form a node electrode, is still a semiconductor, and not as conductive as a low resistivity metal fill.
Metals and their suicides are of greater conductivity, and various silicides of metals have been proposed for use as node electrodes, including the silicides of titanium (TiSi
2
), zirconium (ZrSi
2
), chromium (CrSi
2
), molybdenum (MoSi
2
), tungsten (WSi
2
), nickel (NiSi
2
) and cobalt (CoSi
2
). But when a metal or silicide is used as a node electrode in conjunction with a buried plate outdiffusion, a workfunction difference results, requiring the back bias on the buried plate to be changed to a potential which is not halfway between the low and high node potentials. Such altered back bias, as indicated above, is less desirable because it may lead to lower signal margins and higher leakage currents.
Not only the node electrode but the buried plate electrode, as well, requires low resistivity, because of the increasingly small cross section of the trench, and the switching speeds at which node potentials are driven. Gas phase As-doped silicon typically used in trench capacitor formation has resistivities on the order of 4.5 milliohms-cm, which corresponds to an As concentration of about 1×10
20
Atoms/cm
3
. This As concentration is approaching the solid solubility limit of As in silicon at room temperature. Thus, further improvements are not foreseen in the resistivity of the buried plate when formed as an outdiffusion of As ions into silicon.
Therefore, a new method and structure is needed for trench capacitors that lowers buried plate resistivity, and improves the capacitance of the storage node.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a structure and method for the formation of a buried plate capacitor electrode in a semiconductor substrate, where the plate is self-aligned with respect to a dielectric insulating collar in the upper region of the trench.
Another object of the invention is to provide a structure and method for forming a trench capacitor including a buried plate electrode having a low resistivity.
Another object of the present invention is to enable the introduction of a metal-insulator-metal (MIM) capacitor materials system in the trench storage capacitor where one of the metal electrodes is formed by salicide reaction between the silicon substrate and a metal.
Another object of the invention is to provide a trench capacitor having increased node capacitance by forming a buried plate electrode in a silicide layer which lines the sidewalls and bottom of a deep trench capacitor.
These and other objects are provided by the present method of fabricating a buried plate electrode within a trench cell capacitor of a semiconductor substrate, including forming a trench within a semiconductor substrate; forming an oxide collar in an upper portion of the trench; depositing a conformal metal film to cover a lower portion of the trench and the oxide collar; annealing the semiconductor substrate to form a self-aligned silicide layer in the lower portion of the trench; and selectively removing all or portions of the conformal metal film from an upper portion of the trench including the oxide collar.
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IBM Technical Disclosure Bulletin, “Shared trench one-device dynamic random-access memory cell”, vol. 31, No. 7, Dec. 1988, pp. 307-308.
IBM Technical Disclosure Bulletin, “Groove-trench MIS capacitor”, N. C. C. Lu, vol. 26, No. 2, Jul. 1983, pp. 489-490.
Chudzik Michael Patrick
Jammy Rajarao
Mandelman Jack Allan
Radens Carl John
Settlemyer, Jr. Kenneth T.
Abate Joseph P.
Fahmy Wael
Neff Daryl K.
Pham Hoai
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