Method and structure for refresh operation with a low voltage of

Details Method and structure for refresh operation with a low voltage of Method and structure for refresh operation with a low voltage of

1998-06-01

2000-08-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Precharge

365222, G11C 700

Patent

active

060976497

ABSTRACT:
A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.0 V without compromising the reliability of the sense amplifier. The implementation of the method and structure of the present invention is cost effective and practical for most if not all DRAM applications.

REFERENCES:
patent: 5339274 (1994-08-01), Dhong et al.
patent: 5844832 (1998-12-01), Kim
patent: 5892728 (1999-04-01), Allen et al.

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