Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-06
2001-12-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S655000, C438S659000, C438S664000, C438S768000, C438S658000
Reexamination Certificate
active
06331486
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to complementary metal oxide semiconductor (CMOS) manufacturing, and more particular to a method for reducing contact resistance of a metal silicide contact by using a metal germanium alloy as the starting material for the metal silicide.
BACKGROUND OF THE INVENTION
As the dimensions in complementary metal oxide semiconductor (CMOS) devices are continually reduced, the drive current in such devices becomes limited by the parasitic series resistance of the ohmic contacts. The reduction in contact hole area drives the search for materials that can form an ohmic contact with very low resistivity.
One type of material commonly employed in fabricating ohmic contacts is metal silicides such as cobalt silicide. Cobalt silicide and other metal silicides are typically fabricated using a conventional self-aligned silicide (salicide) process, wherein a blanket TiN/Co film is deposited over the devices and annealed to form cobalt monosilicide over the exposed silicon regions (source, drain and gate) of transistors. A selective wet etch is employed to remove the TiN cap and the non-reacted cobalt left over the oxide or nitride regions. The cobalt monosilicide is then subjected to a second anneal which converts the monosilicide into a cobalt disilicide layer.
Although silicides of Ti, Co and Ni offer some of the properties needed to this point, an improvement in resistance of the ohmic contact is definitely needed for future generation of devices.
The Schottky barrier heights of a given material on n+ and p+ silicon substrates must add to 1.13 eV, the band gap of silicon. It is difficult however to find a material that lowers the contact resistance to both p-type and n-type material.
One obvious solution to the above problem is to use different materials for n- and p-type areas of a circuit. This, however, is not a financially suitable solution since it adds many additional processing steps to the overall fabrication scheme.
In view of the above-mentioned drawbacks with prior art processes, there is a continued need for developing a new and improved method of reducing contact resistance of metal silicides to at least the p+Si area of the substrate.
SUMMARY OF THE INVENTION
The present invention provides a method which overcomes the above mentioned drawbacks with prior art salicide processes. This is achieved in the present invention by utilizing Co—Ge, Ti—Ge, Ni—Ge or mixtures thereof (herein referred to as metal germanium alloys) as a starting material for fabricating metal silicide contacts. The use of the aforementioned metal Ge alloys significantly reduces the contact resistance of silicide contacts to the p+ nsilicon area or the n+ silicon area of the substrate. Such reduction in contact resistance has not been observed utilizing any prior art process known to applicants; therefore the present invention provides a significant advancement in the art of fabricating CMOS devices having low resistivity ohmic contacts.
Specifically, the method of the present invention which is capable of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprises the steps of:
(a) forming a metal germanium (Ge) alloy layer over a silicon-containing substrate, wherein said metal of said alloy layer is selected from the group consisting of Co, Ti, Ni and mixtures thereof;
(b) optionally forming an oxygen barrier layer over said metal germanium alloy layer;
(c) annealing said metal germanium alloy layer at a temperature which is effective in converting at least a portion thereof into a metal silicide layer that is substantially non-etchable compared to the unreacted metal germanium alloy layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer;
(d) removing said optional oxygen barrier layer and any remaining metal Ge alloy layer, with the proviso that when Co and Ti are employed, a second annealing step is employed after the removing step which converts the substantially non-etchable metal silicide layer into Co disilicide or the C54 phase of TiSi
2
, i.e., lowest resistance silicide phases of Co and Ti, respectively.
In an optional embodiment of the present invention and when Co is employed, a pre-annealing step is carried out between steps (a) and (c) or (b) and (c) at an annealing temperature which is sufficient to form a metal rich germanium silicide phase layer in the structure. Typically, the pre-annealing step is carried out at a temperature that is lower than the temperature used in forming the etch resistant metal silicide layer and the Si—Ge interlayer.
When Ni is employed as the metal, Ni monosilicide is formed after a single annealing step. Not only is Ni monosilicide etch resistant, but it represents the lowest resistance silicide phase of Ni. On the other hand, when Co and Ti are employed, two annealing steps are required in forming the lowest resistance silicide phase. For example, when Co is employed, the first annealing step converts the Co—Ge alloy layer into a Co monosilicide layer (a substantially non-etchable, high resistance silicide phase of Co) and thereafter a second annealing step is used to convert the substantially non-etchable silicide phase into a Co disilicide phase (lowest resistance phase of Co silicide). In the case of Ti, the first anneal forms the C49 phase of TiSi
2
(a substantially non-etchable, high resistance Ti silicide phase) and the second anneal converts the etch resistant silicide phase into a C54 phase (lowest resistance disilicide phase of Ti). When the second anneal is employed, the second annealing step is carried out at a temperature that is greater than the temperature used to form the substantially non-etchable metal silicide, i.e., Co monosilicide or the C49 phase of TiSi
2
. It should be noted that the term “substantially non-etchable” denotes a material that is difficult to etch in the etchant solutions mentioned hereinbelow; the material is more difficult to etch than the unreacted metal germanium alloy layer.
Another aspect of the present invention relates to low resistivity electrical contacts that are formed utilizing the method of the present invention. In accordance with one aspect of the present invention, a low resistance electrical contact to a region of a silicon-containing substrate is provided that comprises: a substrate having an exposed region of a silicon-containing semiconductor material and a first layer of a metal silicide being in its lowest resistance phase, wherein said metal is selected from the group consisting of Ni, Co, Ti and mixtures thereof, and said substrate and said first layer are separated by a Si—Ge interlayer.
When Ni is employed, the metal silicide contact is composed mainly of the monosilicide phase, when Co is employed, the metal silicide contact is composed mainly of the disilicide phase; and, when Ti is employed, the metal silicide contact is composed mainly of the C54 phase of TiSi
2
. Each of the above mentioned phases, represent the lowest resistance phase of the metal silicide.
REFERENCES:
patent: 4965645 (1990-10-01), Solomon
patent: 5336903 (1994-08-01), Ozturk et al.
patent: 5401674 (1995-03-01), Anjum et al.
patent: 5510295 (1996-04-01), Cabral, Jr. et al.
patent: 5608226 (1997-03-01), Yamada et al.
patent: 5624869 (1997-04-01), Agnello et al.
patent: 5828131 (1998-10-01), Cabral, Jr. et al.
Huang et al. “Impact of Ge implantation on the electrical characteristics of TiSi2 p+n shallow junctions with an a-Si (or poly-Si) buffer layer” in IEEE Transactions on Electron Devices, 44(4), Apr. 1997, pp. 601-606.*
Prabhakaran et al. “Diffusion mediated chemical reaction in Co/Ge/Si(100) forming Ge/CoSi2/Si(100)” in Applied Physics Letters 68(9), Feb. 26, 1996, pp. 1241-1243.*
M. Lawrence, et al., “Growth of Epitaxial CoSi2on (100)Si,” Appl. Phys. Lett., vol. 58, No. 12, pp. 1308-1310 (1991).
C. Cabral, et al., “In-Situ X-Ray Diffractin and Resistivity Analysis of CoSi2 Phase Fo
Cabral, Jr. Cyril
Carruthers Roy Arthur
Harper James McKell Edwin
Lavoie Christian
Roy Ronnen Andrew
Bowers Charles
International Business Machines - Corporation
Kielin Erik
Scully Scott Murphy & Presser
Trepp, Esq. Robert M.
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