Method and structure for reducing induced mechanical stresses

Details Method and structure for reducing induced mechanical stresses Method and structure for reducing induced mechanical stresses

2007-11-09

2009-08-11

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S199000, C257S396000, C257SE21632, C257SE27108

Reexamination Certificate

active

07572689

ABSTRACT:
Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

REFERENCES:
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patent: 2005/0148134 (2005-07-01), Dokumaci et al.

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