Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-09-11
2007-09-11
Smith, Bradley K. (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21585
Reexamination Certificate
active
11088311
ABSTRACT:
An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.
REFERENCES:
patent: 5057888 (1991-10-01), Fazan et al.
patent: 5250457 (1993-10-01), Dennison
patent: 5292677 (1994-03-01), Dennison
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5401681 (1995-03-01), Dennison
patent: 5488011 (1996-01-01), Figura et al.
patent: 5554557 (1996-09-01), Koh
patent: 5714778 (1998-02-01), Yamazaki
patent: 5940714 (1999-08-01), Lee et al.
patent: 5998257 (1999-12-01), Lane et al.
patent: 6046093 (2000-04-01), DeBoer et al.
patent: 6083803 (2000-07-01), Fischer et al.
patent: 6083831 (2000-07-01), Dennison
patent: 6174767 (2001-01-01), Chi
patent: 6184079 (2001-02-01), Lee
patent: 6204143 (2001-03-01), Roberts et al.
patent: 6221711 (2001-04-01), Roberts et al.
patent: 6222222 (2001-04-01), DeBoer et al.
patent: 6365453 (2002-04-01), Deboer et al.
patent: 6417065 (2002-07-01), Wu et al.
patent: 6469336 (2002-10-01), Deboer et al.
patent: 6670238 (2003-12-01), Deboer et al.
patent: 6677636 (2004-01-01), Deboer et al.
patent: 6720609 (2004-04-01), Deboer et al.
patent: 6852579 (2005-02-01), Kumauchi et al.
patent: 6878587 (2005-04-01), Deboer et al.
patent: 2003/0148603 (2003-08-01), Gardner
Sakao et al., “A Capacitor-Over-Bit-Line (COB) Cell With a Hemispherical-Grain Storage Node For 64 Mb DRAMs,” IEDM, vol. 90, San Francisco, Dec. 9-12, 1990, pp. 27.3.1-27.3.4.
Agarwal Vishnu K.
Deboer Scott J.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Smith Bradley K.
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