Method and structure for providing tuned leakage current in...

Details Method and structure for providing tuned leakage current in... Method and structure for providing tuned leakage current in...

2007-09-11

2007-09-11

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21443

Reexamination Certificate

active

11340354

ABSTRACT:
A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.

REFERENCES:
patent: 3328210 (1987-06-01), Mccaldin et al.
patent: 4827324 (1989-05-01), Blanchard
patent: 5264380 (1993-11-01), Pfiester
patent: 5321283 (1994-06-01), Cogan et al.
patent: 6509233 (2003-01-01), Chang et al.
patent: 2002/0123196 (2002-09-01), Chang et al.
patent: 2004/0178438 (2004-09-01), Mitros et al.
patent: 2004/0195628 (2004-10-01), Wu et al.
patent: 2005/0020020 (2005-01-01), Collaert et al.

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