Method and structure for metal-insulator-metal capacitor...

Details Method and structure for metal-insulator-metal capacitor... Method and structure for metal-insulator-metal capacitor...

2007-03-13

2007-03-13

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S244000, C438S253000, C438S386000, C438S387000, C438S396000, C257S300000, C257S303000, C257S306000, C257S516000, C257S532000

Reexamination Certificate

active

11064894

ABSTRACT:
A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose an inter-metal dielectric layer adjacent to the second conductive layer in the memory cell region. The exposed inter-metal dielectric layer is etched off to form an opening adjacent to the second conductive layer. A capacitor dielectric layer and third conductive layer are formed on inner walls of the opening to constitute a metal-insulator-metal capacitor.

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