Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2002-12-31
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C257S375000, C257S316000
Reexamination Certificate
active
06500714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor process, and particularly to a method and a structure for manufacturing ROMs requiring a shorter delivery time in a semiconductor process.
2. Description of the Related Art
FIG. 1
is a circuit diagram showing a traditional ROM, wherein reference symbols BL
1
~BL
4
, WL
1
~WL
4
and
0
and
1
represent N
+
-type bit lines, word lines and program codes, respectively.
FIG. 2
is a top view showing the structure of the traditional ROM of FIG.
1
. In
FIG. 2
, reference symbols
10
,
12
, BL
1
~BL
4
and WL
1
~WL
4
represent a P-type substrate, code implanted regions, N
+
-type bit lines and gates (word lines), respectively. Generally, in a ROM process according to the prior art, a plurality of N
+
-type barrier layers (N
+
-type bit lines) BL
1
~BL
4
are first formed under the surface of the P-type substrate
10
by photolithography and ion implantation. A plurality of gates (word lines) WL
1
~WL
4
are formed on the P-type substrate
10
by photolithography, chemical vapor deposition and plasma etching, wherein each gate consists of a first oxide layer, a polysilicon layer and a second oxide layer (not shown) from the bottom to the top, and the plurality of word lines WL
1
~WL
4
are perpendicular to the plurality of N
+
-type bit lines BL
1
~BL
4
. Next, nitride spacers (not shown) are formed on both sides of each word line. Based on the program codes provided by a client, code implanted regions
12
are formed by ion implantation. Consequently, an inter-layer oxide (not shown) is formed on the P-type substrate
10
, bit lines BL
1
~BL
4
, word lines WL
1
~WL
4
by chemical vapor deposition. A plurality of contact windows (not shown) are formed in the inter-layer oxide over the N
+
-type bit lines BL
1
~BL
4
. Thereafter, a patterned aluminum layer (not shown) is formed on the inter-layer layer and contact windows by photolithography, chemical vapor deposition and plasma etching. Finally, a passivation (not shown) is formed on the inter-layer oxide and the patterned aluminum layer.
In the prior ROM process mentioned-above, due to limitations of implanting energy and threshold control, the program codes must be implanted before the inter-layer oxide layer is formed. This lengthens the delivery time of the process.
SUMMARY OF THE INVENTION
In view of the above, the objective of the invention is to provide a method for manufacturing ROMs requiring a shorter delivery time in a semiconductor process. The method for manufacturing ROMs according to the invention, suitable for a substrate, comprises the following steps: First, a plurality of first bit lines are formed under the surface of the substrate by ion implantation. Then, a plurality of gates, each of which consists of a first dielectric layer, a polysilicon layer and a second dielectric layer from the bottom to the top, are formed on the substrate, wherein the gates are perpendicular to said first bit lines. After that, spacers are formed on both sides of each gate. A plurality of second bit lines, parallel to the first bit lines, are formed under the surface of the substrate, wherein each second bit line is discrete under the gates. Next, a third dielectric layer is formed on the substrate, the first bit lines, the second bit lines and the gates. Based on the program codes provided by a client, a plurality of contact windows are formed in the third dielectric layer over each first bit line and corresponding parts of each second bit line, thereby completely setting up the required program codes. Finally, a conductor is formed on the third dielectric layer and the contact windows, then patterning the conductor.
According to the method for manufacturing ROMs of the invention, since each second bit line is discrete under the gates, the program codes provided by a client can be set up by forming a plurality of contact windows in the third dielectric layer over corresponding parts of each second bit line. That is, a logic level “1” or “0” stored in each memory unit is determined by whether there is a corresponding contact window. As can be known from the above, the program codes and contact windows are formed at the same time by using only one mask. Therefore, delivery time of the process is greatly shortened.
REFERENCES:
patent: 5712500 (1998-01-01), Hsue et al.
patent: 5721442 (1998-02-01), Hong
Berry Rene′ R
Ladas & Parry
Nelms David
Windbond Electronics Corp.
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