Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-15
2001-10-02
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C257S301000
Reexamination Certificate
active
06297151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor process, and in particular to a method and structure for manufacturing contact windows between different levels of conductive layers in the semiconductor process. The method is suitable for manufacturing contact windows between the capacitors used for storing charges and interconnection layers or between different levels of conductive layers inside the memory cells of a dynamic random access memory (hereinafter referred to as “DRAM”). The structure of a contact window manufactured by means of the above-mentioned method can provide greater contact area between said capacitor and interconnection layer, thereby reducing the contact resistance thereof.
2. Description of Prior Art
Capacitors are very common components of semiconductor devices. Storage capacitors are especially widely utilized in DRAM memory cells. Generally, the DRAM memory cells consist of access transistors serving as switching devices, and storage capacitors. The gates of the access transistors are controlled by bit-lines. The sources and drains of the access transistors are connected to the storage capacitors and bit-lines, respectively. In addition, the other electrodes of the storage capacitors must be connected to other regions via an interconnection layer.
FIG. 1
is a flow chart illustrating a method for manufacturing a capacitor of a typical memory cell. The capacitor manufacturing according to the prior art will be described in FIG.
1
. First, a substrate on which MOS (Metal-Oxide-Semiconductor) devices are already formed, is provided, wherein the MOS devices consist of gates, as well as sources and drains which are formed on the two sides of the gates, respectively (S
1
). According to the structure of the typically DRAM memory cell, a first insulating layer is deposited on the MOS devices, thereby separating the MOS devices from subsequently-formed capacitors, wherein the capacitors will be connected to the sources of the MOS devices (S
2
). First contact windows are formed on the first insulating layer for providing contact paths between the sources of the MOS devices and the subsequently-formed capacitors (S
3
). A first conductive layer for the capacitors is formed on the first insulating layer and first contact windows, so that the first conductive layer can be connected to the sources of the MOS devices via the first contact windows (S
4
). The first conductive layer is etched, thereby defining the shape and size of the capacitors (S
5
). After defining the dimensions of the capacitors, a dielectric layer and second conductive layer are formed in order on the first conductive layer by a deposition process (S
6
), so that the capacitors are completely fabricated. In general, in order to maintain high capacitance of the capacitors, the thickness of the dielectric layer should be minimized and the areas of the first conductive layer and second conductive layer should be maximized. After completing the above step, the required connection between the second conductive layer and interconnection layer is formed.
Similarly, a second insulating layer is formed on the second conductive layer of the capacitors, thereby separating the capacitors from a subsequently-formed interconnection layer (S
7
). Then, second contact windows are formed on appropriate positions (i.e., the regions which are separate from the capacitors and MOS devices) of the second insulting layer by an etching process in order to provide connection paths between the second conductive layer and the subsequently-formed interconnection layer (S
8
). Finally, an interconnection layer is formed on the second insulating layer and second contact windows, so that the interconnection layer can be connected to the second conductive layer of the capacitors via the second contact windows (S
9
).
In the S
8
, the contact areas between the interconnection layer and the second conductive layer can be controlled by the etching depth of the second insulting layer. Referring to
FIG. 2
, there is shown a cross-sectional view illustrating a contact window between the interconnection layer and the second conductive layer of a capacitor in accordance with a first example of the prior art. In the
FIG. 2
, the numerals
1
,
2
,
3
,
5
and
7
represent a first insulating layer, a dielectric layer of the capacitor, a second conductive layer of the capacitor, a second insulating layer and an interconnection layer, individually. It should be noted that the cross-sectional view in
FIG. 2
does not show a position on which the capacitor is formed, but it is the position of a second contact window
6
via which the capacitor and the first conductive layer
7
are connected each other. Furthermore, part of the first conductive layer of the capacitor on this position is removed during S
5
of defining the dimensions of the capacitor.
It is evident from
FIG. 2
that part of the second conductive layer
3
of the capacitor is removed during an etching process to the insulating layer
5
in order to form the contact window
6
. This is caused by there being different etching depth requirements for the contact windows at the same time. Generally, the contact window
6
in
FIG. 2
belongs to a region on which an insulating layer need to be etched more thinly, while the source and drain of the MOS device belong to another region on which an insulating layer need to be etched more deeply. Therefore, deep etching is used in this process due to the region that needs to be etched deeply. Accordingly, part of the second conductive layer
3
of the capacitor is removed during the etching process, hence what is called overetching occurs. However, this over-etching may not in fact be deleterious. Taking
FIG. 2
as an example, since the bottom of the contact window
6
does not cross the second conductive layer
3
, this over-etching can actually increase the contact area between the interconnection layer
7
and the second conductive layer
3
. The additional contact area is contributed by the side walls of the contact window which contact with the second conductive layer
3
. Typically, the enlarged contact area means that the contact resistance between the second conductive layer
3
and the interconnection layer
7
is decreased.
However, such over-etching phenomena contains uncertainties ties. Although it can increase the contact area of the contact window under some circumstances, it may also greatly reduce the contact area under other circumstances.
FIG. 3
is a cross-sectional view showing the contact window between a interconnection layer and a second conductive layer of a capacitor in accordance with a second example of the prior art. In this example, since the bottom of the contact window
6
a
crosses the dielectric layer
2
, and even reaches to the second conductive layer
1
, the contact area on the bottom of the contact window
6
a
is lost. Therefore, the inherent uncertainty of over-etching may increase the contact area or reduce the contact area depending on different circumstances.
In the prior art, the etching stopper is generally formed beneath the second conductive layer, thereby preventing the contact window from crossing the second conductive layer
3
of the capacitor. For example, in U.S. Pat. No. 4,754,318 “Semiconductor device”, Momose et al., the same method is disclosed. However, the disadvantages of the above-mentioned method are that the cost is increased and excessive production processes are required. If the factors of cost and efficiency are taken into account, the method according to the prior art is not the best way to prevent decreasing the contact area.
As described above, the contact area can be increased under some over-etching circumstances. However, the method according to the prior art does not have this advantage. Therefore, the method of manufacturing the capacitor and contact window need to be modified so as to obtain the best performance.
Similarly, the same problem will be caused at the contact window between different levels of con
Chang Julian Y.
Chuang Da-Zen
Fish & Richardson P.C.
Nan Ya Technology Corporation
Wilson Christian D.
Zarabian Amir
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