Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-06-19
1998-12-15
Booth, Richard A.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438296, H01L 2176
Patent
active
058496211
ABSTRACT:
A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.
REFERENCES:
patent: 4506434 (1985-03-01), Ogawa et al.
patent: 4532696 (1985-08-01), Iwai
patent: 4683637 (1987-08-01), Varker et al.
patent: 4980306 (1990-12-01), Shimbo
patent: 5015601 (1991-05-01), Yoshikawa
patent: 5282160 (1994-01-01), Yamagata
patent: 5387534 (1995-02-01), Prall
patent: 5424569 (1995-06-01), Prall
patent: 5614430 (1997-03-01), Liang et al.
patent: 5741735 (1998-04-01), Violette et al.
International Search Report for PCT/US 97/02492 dated Jun. 11, 1997.
Fulford Jr. H. Jim
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Booth Richard A.
Daffer Kevin L.
Kowert Robert C.
LandOfFree
Method and structure for isolating semiconductor devices after t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for isolating semiconductor devices after t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for isolating semiconductor devices after t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1457297