Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2007-01-30
2007-01-30
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S438000, C438S774000, C438S761000
Reexamination Certificate
active
10986984
ABSTRACT:
A method for forming an oxide layer on a vertical, non-planar semiconductor surface provides a low stress oxide layer having a pristine interface characterized by a roughness of less than 3 angstroms. The oxide layer includes a portion that is substantially amorphous and notably dense. The oxide layer is a graded growth oxide layer including a composite of a first oxide portion formed at a relatively low temperature below the viscoelastic temperature of the oxide film and a second oxide portion formed at a relatively high temperature above the viscoelastic temperature of the oxide film. The process for forming the oxide layer includes thermally oxidizing at a first temperature below the viscoelastic temperature of the film, and slowly ramping up the temperature to a second temperature above the viscoelastic temperature of the film and heating at the second temperature. After the second, high temperature oxidation above the viscoelastic temperature, the structure is then slowly cooled under gradual, modulated cooling conditions.
REFERENCES:
patent: 4277320 (1981-07-01), Beguwala et al.
patent: 4518630 (1985-05-01), Grasser
patent: 4826779 (1989-05-01), Wright et al.
patent: 4851370 (1989-07-01), Doklan et al.
patent: 4931409 (1990-06-01), Nakajima et al.
patent: 5016081 (1991-05-01), Brown et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5089441 (1992-02-01), Moslehi
patent: 5153701 (1992-10-01), Roy
patent: 5210056 (1993-05-01), Pong et al.
patent: 5334556 (1994-08-01), Guldi
patent: 5371394 (1994-12-01), Ma et al.
patent: 5464783 (1995-11-01), Kim et al.
patent: 5514608 (1996-05-01), Williams et al.
patent: 5567638 (1996-10-01), Lin et al.
patent: 5598369 (1997-01-01), Chen et al.
patent: 5619052 (1997-04-01), Chang et al.
patent: 5622607 (1997-04-01), Yamazaki et al.
patent: 5629221 (1997-05-01), Chao et al.
patent: 5707888 (1998-01-01), Aronowitz et al.
patent: 5739580 (1998-04-01), Aronowitz et al.
patent: 5757204 (1998-05-01), Nayak et al.
patent: 5814562 (1998-09-01), Green et al.
patent: 5817581 (1998-10-01), Bayer et al.
patent: 5821158 (1998-10-01), Shishiguchi
patent: 5851892 (1998-12-01), Lojek et al.
patent: 5863831 (1999-01-01), Ling et al.
patent: 5867425 (1999-02-01), Wong
patent: 5869405 (1999-02-01), Gonzalez et al.
patent: 5877057 (1999-03-01), Gardner et al.
patent: 5885870 (1999-03-01), Maiti et al.
patent: 5891809 (1999-04-01), Chau et al.
patent: 5913149 (1999-06-01), Thakur et al.
patent: 5918137 (1999-06-01), Ng et al.
patent: 5926741 (1999-07-01), Matsuoka et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5968279 (1999-10-01), MacLeish et al.
patent: 5972804 (1999-10-01), Tobin et al.
patent: 6008128 (1999-12-01), Habuka et al.
patent: 6020247 (2000-02-01), Wilk et al.
patent: 6025280 (2000-02-01), Brady et al.
patent: 6027975 (2000-02-01), Hergenrother et al.
patent: 6029680 (2000-02-01), Hawthorne et al.
patent: 6069062 (2000-05-01), Downey
patent: 6083815 (2000-07-01), Tsai et al.
patent: 6083836 (2000-07-01), Rodder
patent: 6180454 (2001-01-01), Chang et al.
patent: 6197641 (2001-03-01), Hergenrother et al.
patent: 6207591 (2001-03-01), Aoki et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6222233 (2001-04-01), D'Anna
patent: 6281140 (2001-08-01), Chen et al.
patent: 6281559 (2001-08-01), Yu et al.
patent: 6316300 (2001-11-01), Ozeki et al.
patent: 6492712 (2002-12-01), Chen et al.
patent: 6541394 (2003-04-01), Chen et al.
patent: 0 301 460 (1989-02-01), None
patent: 0 323 071 (1989-07-01), None
patent: 2 056 174 (1981-03-01), None
patent: 2 347 265 (2000-08-01), None
patent: 62 079 628 (1987-04-01), None
patent: 01 204435 (1989-08-01), None
patent: WO 96/33510 (1996-10-01), None
Ponomarev et al.; High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates; IEEE Transactions on Electron Devices, vol. 47, No. 4; Apr. 2000; pp. 848.
Lee et al.; Enhancement of PMOS Device Performance with Poly-SiGe Gate; Electron Device Letters, vol. 20, No. 5; May 1999; pp. 232-234.
Song et al.; Ultra Thin (<20) CVD Si3N4 Gate Dielectric for Song et al.; Ultra Thin (<20) CVD Si3N4 Gate Dielectric for Deep-Sub-Micron CMOS Devices; Microelectronics Research Center, The University of Texas, Austin; 4 pgs.
Hattangady et al.; Ultrathin nitrogen-profile engineered gate dielectric films; Semiconductor Process and Device Center, Texas Instruments; 4 pgs.
Tseng et al.; Reduced Gate Leakage Current and Boron Penetration of 0.18 m 1.5 V MOSFETs using Integrated RTCVD Oxynitride Gate Dielectric; 4 pgs.
Hattangady et al.; Remote Plasma Nitrided Oxides for Ultrathin Gate Dielectric Applications; SPIE 1998 Symp. Microelec. Manf.; Sep. 1998; Santa Clara, CA; pp. 1-11.
Wu et al.; Improvement of Gate Dielectric Reliability for p+ Poly MOS Devices Using Remote PECVD Top Nitride Deposition on Thin Gate Oxides; IEEE 98 36th Annual International Reliability Physics Symposium; Reno, Nevada; 1998; pp. 70-75.
Chatterjee et al.; Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process; Semiconductor Process and Device Center, Texas Instruments; 1997 IEEE; 4pgs.
Kraft et al.; Surface nitridation of silicon dioxide with a high density with nitrogen plasma; J. Vac. Scl. Technol. B, vol. 15, No. 4; 1997 American Vacuum Society; Jul./Aug. 1997; pp. 967-970.
Jeon et al.; Low Temperature of SiO2 Films With Low Interface Trap Density Using ECR Diffusion and ECR CVD Methods; 1996 Conference on Optoelectronic and Microelectronic Materials and Devices Proceedings, Canberra, ACT, Australia, 8-11 Dec. 1996; pp. 259-262.
Rau et al.; Characterization of stacked gate oxides by electron holography; Appl. Phys. Lett., vol. 68, No. 24; 1996 American Institute of Physics; Jun. 10, 1996; pp. 3410-3412.
Ghandhi; VLSI Fabrication Principles—Silicon and Gallium Arsenide; Second Edition; John Wiley & Sons, Inc.; 1994; p. 453.
Cramer et al.; Sodium passivation dependence on phosphorous concentration in tetraethylorthosilicate plasma-enhanced chemical vapor deposited phosphosilicate glasses; J. Appli. Phys. vol. 73, No. 5; 1993 American Institute of Physics; Mar. 1, 1993; pp. 2458-2461.
Wolf; Silicon Processing For The VLSI Era; vol. 2: Process Integration; Lattice Press, Sunset Beach, California; 1990; pp. 354-361.
Wolf; Silicon Processing For The VLSI Era; vol. 1: Process Technology; Lattice Press, Sunset Beach, California; 1986; pp. 5.
Chaudhry Samir
Roy Pradip K.
Agere Systems Inc.
Trinh Michael
LandOfFree
Method and structure for graded gate oxides on vertical and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for graded gate oxides on vertical and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for graded gate oxides on vertical and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3803341