Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-09-13
2009-06-23
Smoot, Stephen W (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C257SE21618
Reexamination Certificate
active
07550338
ABSTRACT:
A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5241197 (1993-08-01), Murakami et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy
patent: 5592007 (1997-01-01), Leedy
patent: 5592018 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5840593 (1998-11-01), Leedy
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5946559 (1999-08-01), Leedy
patent: 5960297 (1999-09-01), Saki
patent: 5989978 (1999-11-01), Peidous
patent: 6008126 (1999-12-01), Leedy
patent: 6025280 (2000-02-01), Brady et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6165383 (2000-12-01), Chou
patent: 6221735 (2001-04-01), Manley et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6246095 (2001-06-01), Brady et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6284626 (2001-09-01), Kim
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6403486 (2002-06-01), Lou
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6423615 (2002-07-01), Ravi et al.
patent: 6461936 (2002-10-01), Von Ehrenwall
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6703293 (2004-03-01), Tweet et al.
patent: 6703648 (2004-03-01), Xiang et al.
patent: 6717216 (2004-04-01), Doris et al.
patent: 6787423 (2004-09-01), Xiang
patent: 6825086 (2004-11-01), Lee et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 6891192 (2005-05-01), Chen et al.
patent: 6974981 (2005-12-01), Chidambarrao et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 7015082 (2006-03-01), Doris et al.
patent: 7129126 (2006-10-01), Steegen et al.
patent: 2001/0003364 (2001-06-01), Sugawara et al.
patent: 2001/0009784 (2001-07-01), Ma et al.
patent: 2001/0045604 (2001-11-01), Oda et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0086497 (2002-07-01), Kwok
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2002/0142566 (2002-10-01), Ravi et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0057184 (2003-03-01), Yu et al.
patent: 2003/0067035 (2003-04-01), Tews et al.
patent: 2003/0087492 (2003-05-01), Lee et al.
patent: 2003/0148584 (2003-08-01), Roberds et al.
patent: 2004/0188760 (2004-09-01), Skotnicki et al.
patent: 2004/0238914 (2004-12-01), Deshpande et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0082634 (2005-04-01), Doris et al.
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2005/0098829 (2005-05-01), Doris et al.
patent: 2005/0106799 (2005-05-01), Doris et al.
patent: 2005/0145954 (2005-07-01), Zhu et al.
patent: 2005/0148146 (2005-07-01), Doris et al.
patent: 2005/0194699 (2005-09-01), Belyansky et al.
patent: 2005/0236668 (2005-10-01), Zhu et al.
patent: 2005/0245017 (2005-11-01), Belyansky et al.
patent: 2005/0280051 (2005-12-01), Chidambarrao et al.
patent: 2005/0282325 (2005-12-01), Belyansky et al.
patent: 2006/0027868 (2006-02-01), Doris et al.
patent: 2006/0057787 (2006-03-01), Doris et al.
patent: 2006/0060925 (2006-03-01), Doris et al.
patent: 2 838 237 (2003-10-01), None
patent: 64-76755 (1989-03-01), None
G. Zhang, et al., “A New ‘Mixed-Mode’ Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors.” IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 2002, pp. 2151-2156.
H.S. Momose, et al., “Temperature Dependence of Emitter-Base Reverse Stress Degradation and its Mechanism Analyzed by MOS Structures.” 1989 IEEE, Paper 6.2, pp. 140-143.
C.J. Huang, et al., “Temperature Dependence and Post-Stress Recovery of Hot Electron Degradation Effects in Bipolar Transistors.” IEEE 1991, Bipolar Circuits and Technology Meeting 7.5, pp. 170-173.
S.R. Sheng, et al., “Degradation and Recovery of SiGe HBTs Following Radiation and Hot-Carrier Stressing.” pp. 14-15.
Z. Yang, et al., “Avalanche Current Induced Hot Carrier Degradation in 200 GHz SiGe Heterojunction Bipolar Transistors.” pp. 1-5.
H. Li, et al., “Design of W-Band VCOs with High Output Power for Potential Application in 77 GHz Automotive Radar Systems.” 2003, IEEE GaAs Digest, pp. 263-266.
H. Wurzer, et al., “Annealing of Degraded non-Transistors-Mechanisms and Modeling.” IEEE Transactions on Electron Devices, vol. 41, No. 4, Apr. 1994, pp. 533-538.
B. Doyle, et al., “Recovery of Hot-Carrier Damage in Reoxidized Nitrided Oxide MOSFETs.” IEEE Electron Device Letters, vol. 13, No. 1, Jan. 1992, pp. 38-40.
H.S. Momose, et al. “Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for Bi-CMOS.” IEEE Transactions on Electron Devices, vol. 41, No. 6, Jun. 1994, pp. 978-987.
M. Khater, et al., “SiGe HBT Technology with Fmax/Ft = 350/300 GHz and Gate Delay Below 3.3 ps”. 2004 IEEE, 4 pages.
J.C. Bean, et al., “GEx SI 1-x/Si Strained-Layer Superlattice Grown by Molecular Beam Epitaxy”. J. Vac. Sci. Technol. A 2(2), Apr.-Jun. 1984, pp. 436-440.
J.H. Van Der Merwe, “Regular Articles”. Journal of Applied Physics, vol. 34, No. 1, Jan. 1963, pp. 117-122.
J.W. Matthews, et al., “Defects in Epitaxial Multilayers”. Journal of Crystal Growth 27 (1974), pp. 118-125.
Subramanian S. Iyer, et al. “Heterojunction Bipolar Transistors Using Si-Ge Alloys”. IEEE Transactions on Electron Devices, vol. 36, No. 10, Oct. 1989, pp. 2043-2064.
R.H.M. Van De Leur, et al., “Critical Thickness for Pseudomorphic Growth of Si/Ge Alloys and Superlattices”. J. Appl. Phys. 64(6), Sep. 15, 1988, pp. 3043-3050.
D.C. Houghton, et al.
Steegen An L.
Yang Haining S.
Zhang Ying
Abate Joseph P.
Greenblum & Bernstein P.L.C.
International Business Machines - Corporation
Smoot Stephen W
LandOfFree
Method and structure for forming strained SI for CMOS devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for forming strained SI for CMOS devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for forming strained SI for CMOS devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4062577