Method and structure for forming strained Si for CMOS devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S221000, C438S739000

Reexamination Certificate

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07129126

ABSTRACT:
A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5241197 (1993-08-01), Murakami et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy
patent: 5592007 (1997-01-01), Leedy
patent: 5592018 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5840593 (1998-11-01), Leedy
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5946559 (1999-08-01), Leedy
patent: 5960297 (1999-09-01), Saki
patent: 5989978 (1999-11-01), Peidous
patent: 6008126 (1999-12-01), Leedy
patent: 6025280 (2000-02-01), Brady et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6165383 (2000-12-01), Chou
patent: 6221735 (2001-04-01), Manley et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6246095 (2001-06-01), Brady et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6284626 (2001-09-01), Kim
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6403486 (2002-06-01), Lou
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6461936 (2002-10-01), von Ehrenwall
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6703293 (2004-03-01), Tweet et al.
patent: 6717216 (2004-04-01), Doris et al.
patent: 6787423 (2004-09-01), Xiang
patent: 6825086 (2004-11-01), Lee et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 6891192 (2005-05-01), Chen et al.
patent: 6974981 (2005-12-01), Chidambarrao et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 7015082 (2006-03-01), Doris et al.
patent: 2001/0003364 (2001-06-01), Sugawara et al.
patent: 2001/0009784 (2001-07-01), Ma et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0086497 (2002-07-01), Kwok
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0057184 (2003-03-01), Yu et al.
patent: 2003/0067035 (2003-04-01), Tews et al.
patent: 2003/0087492 (2003-05-01), Lee et al.
patent: 2004/0238914 (2004-12-01), Deshpande et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0082634 (2005-04-01), Doris et al
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2005/0098829 (2005-05-01), Doris et al.
patent: 2005/0106799 (2005-05-01), Doris et al.
patent: 2005/0145954 (2005-07-01), Zhu et al.
patent: 2005/0148146 (2005-07-01), Doris et al.
patent: 2005/0194699 (2005-09-01), Belyansky et al.
patent: 2005/0236668 (2005-10-01), Zhu et al.
patent: 2005/0245017 (2005-11-01), Belyansky et al.
patent: 2005/0280051 (2005-12-01), Chidambarrao et al.
patent: 2005/0282325 (2005-12-01), Belyansky et al.
patent: 2006/0027868 (2006-02-01), Doris et al.
patent: 2006/0057787 (2006-03-01), Doris et al.
patent: 2006/0060925 (2006-03-01), Doris et al.
patent: 64-76755 (1989-03-01), None
Kern Rim et al., “Transconductance Enhancement in Deep Submicron Strained-Si n-MOSFETs”, International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998, IEDM 98, pp. 707-710.
Kern Rim et al., “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, 2002 Symposium On VLSI Technology Digest of Technical Papers, IEEE, pp 98-99, 2002.
Gregory Scott, et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999, pp. 827-830.
F. Ootsuka, et al., “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Application”, International Electron Devices Meeting, 23.5.1, IEEE, Apr. 2000 pp. 575-578.
Shinya Ito, et al., “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000, pp. 247-250.
A. Shimizu, et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting, IEEE, Mar. 2001, pp. 433-436.
K. Ota, et al., “Novel Locally Strained Channel Technique for high Performance 55nm CMOS”, International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002, pp. 27-30.
G. Zhang, et al., “A New ‘Mixed-Mode’ Reliability Degradation Mechanism in Advanced Si and SiGe Bipolar Transistors.” IEEE Transactions on Electron Devices, vol. 49, No. 12, Dec. 2002, pp. 2151-2156.
H.S. Momose, et al., “Temperature Dependence of Emitter-Base Reverse Stress Degradation and its Mechanism Analyzed by MOS Structures.” 1989 IEEE, Paper 6.2, pp. 140-143.
C.J. Huang, et al., “Temperature Dependence and Post-Stress Recovery of Hot Electron Degradation Effects in Bipolar Transistors,” IEEE 1991, Bipolar Circuits and Technology Meeting 7.5, pp. 170-173.
S.R. Sheng, et al., “Degradation and Recovery of SiGe HBTs Following Radiation and Hot-Carrier Stressing.” pp. 14-15.
Z. Yang, et al., “Avalanche Current Induced Hot Carrier Degradation in 200 GHz SiGe Heterojunction Bipolar Transistors.” pp. 1-5.
H. Li, et al., “Design of W-Band VCOs with High Output Power for Potential Application in 77 GHz Automotive Radar Systems.” 2003, IEEE GaAs Digest, pp. 263-266.
H. Wurzer, et al., “Annealing of D

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