Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-30
2007-10-30
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S938000, C257SE21633
Reexamination Certificate
active
10906669
ABSTRACT:
A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.
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Leobandung Effendi
Zhong Huicai
Zhu Huilong
C. Li Todd M.
Cantor & Colburn LLP
Chaudhari Chandra
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