Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-03-14
2004-01-20
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S665000, C257S223000, C257S306000, C257S521000, C257S530000
Reexamination Certificate
active
06680520
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention generally relates to semiconductor integrated circuits and specifically to a method of fabricating precision circuit elements therein.
In the fabrication of electrical circuits, especially those formed in semiconductor integrated circuits, processing variations often prevent the manufacture of precise components, for example resistors and capacitors. Accordingly, there is a need for a method of trimming devices to obtain the precise values.
Precision capacitors are required in a wide variety of integrated circuit applications. Decoupling capacitors are used for analog V
DD
to ground or analog V
DD
to another power source. Phase-locked-loops (PLL) are another application. Precision capacitors find wide usage in bipolar CMOS RF (radio frequency) applications for wired and wireless telephony and, recently, in series with the input of receivers operating in the gigahertz region.
Trimming of capacitors finds application in A/D and D/A converters where the capacitors need to be matched. Experimentally, it has been shown that in fabricating the capacitors utilizing MOS technology, acceptable ratio matching accuracies of up to 10 bits can be obtained with good yields. However, to achieve accuracy greater than 10 bits, external means such as laser trimming is required to change the size and value of the capacitors as required which, in turn, will increase the typical yield. However, laser trimming is a very expensive and time consuming procedure. Another problem with laser trimming is that it must be performed at the wafer level before the device is packaged. Capacitor precision is affected by stray capacitance induced by the proximity of the packaging material.
Integrated circuit capacitors are formed as metal-insulator-metal capacitors (MIM caps). “Back end of line” (BEOL) refers to the fabrication of the integrated circuit that occurs after the die contacts have been attached. BEOL MIM caps have replaced the very large area silicon capacitors in an effort to save silicon wafer area. However, the MIM caps are not as close to the external package as desired. The closer the precision capacitor to the external package, the better the effectiveness of the MIM capacitor. Another reason the MIM caps are not precision capacitors is due to the high variability in thickness of the deposited insulator (dielectric).
MIM capacitors are used on RF receiver circuits. MIM capacitors are sensitive to electrical overstress (EOS) and electrostatic discharge (ESD) events. MIM capacitors fail at human body model (HBM) ESD events of 100 to 300 Volts. The need to isolate the failing section of the MIM capacitor or eliminate the fail mechanism is important for circuit reliability and yield.
Fuses have been used to aid in compensating for variations in manufactured components. For instance, a fuse may be used to selectively connect additional elements to create the desired output. This has been performed at the wafer level of fabrication of the semiconductor or microcircuit. Once the wafer is diced and packaged the component values are affected. This is particularly true of capacitors which are sensitive to packaging material and other sources of stray capacitance. Therefore, for precision components it is desirable to set the values of the fuses (i.e., open or short) subsequent to packaging.
Accordingly, improvements which overcome any or all of the problems are presently desirable.
BRIEF SUMMARY OF THE INVENTION
The present invention describes an apparatus and method for fabrication of a precision capacitor. In particular, the capacitors are fabricated as part of an integrated circuit assembly. The processing of the capacitor is such to provide a nominal capacitor close in value to the desired value. Additional trim capacitors are joined to the nominal capacitor through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim capacitances are added or subtracted to personalize the nominal capacitor. The links are available for blowing or fusing, as appropriate, at any point in the manufacturing process or packaging level to personalize the capacitance.
Further achieved is the capability of creating a precision capacitor and isolating segments of the precision capacitor which impact yield or fail due to EOS and ESD events. Such capacitor arrangements also provide an opportunity to determine failed capacitor locations for reliability purposes as well as an opportunity of providing redundant capacitors that can be introduced when a capacitor is damaged. This provides a mechanism of salvaging an otherwise irreparable microcircuit in the field.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
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patent: 6011433 (2000-01-01), Nairn
patent: 6191025 (2001-02-01), Liu et al.
Stamper Anthony K.
Voldman Steven H.
Cantor & Colburn LLP
Henkler Richard A.
International Business Machines - Corporation
Nguyen Dilinh
Pham Long
LandOfFree
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