Method and structure for enabling a redundancy allocation...

Details Method and structure for enabling a redundancy allocation... Method and structure for enabling a redundancy allocation...

Filed on

2006-08-01

Date issued

2006-08-01

Examiner

Hoang, Huan (Department: 2827)

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Bad bit

Other Related Categories

C365S201000, C365S230030, C365S189070

Type

Reexamination Certificate

Status

active

Patent number

07085180

Description

ABSTRACT:
A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

REFERENCES:
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patent: 5448523 (1995-09-01), Lewis et al.
patent: 6320800 (2001-11-01), Saito et al.
patent: 6388929 (2002-05-01), Shimano et al.
patent: 6707733 (2004-03-01), Taura et al.
patent: 6757852 (2004-06-01), Ghassemi et al.
patent: 6895537 (2005-05-01), Kawagoe et al.

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