Method and structure for double dose gate in a JFET

Details Method and structure for double dose gate in a JFET Method and structure for double dose gate in a JFET

2006-02-07

2006-02-07

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S136000, C438S138000, C438S186000, C438S192000, C438S303000, C438S305000, C438S570000

Reexamination Certificate

active

06995052

ABSTRACT:
A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

REFERENCES:
patent: 4893160 (1990-01-01), Blanchard
patent: 5349224 (1994-09-01), Gilbert et al.
H. Ogiwara, M. Hayakawa, T. Nishimura and M. Nakaoka; “High-Frequency Induction Heating Inverter With Multi-Resonant Mode Using Newly Developed Normally-Off Type Static Induction Transistors”; Department of Electrical Engineering, Ashikaga Institute of Technology, Japan; Department of Electrical Engineering, Oita University, Japan; Department of Electrical Engineering, Kobe University, Japan; pp. 1017-1023.
J. Baliga; “Highvoltage Junction-Gate Field Effect Transistor With Recessed Gates”; IEEE Transactions on Electron Devices; vol. ED-29; No. 10; Oct. 1982.
J. M. C. Stork et al.; “Small Geometry Depleted Base Bipolar Transistors (BSIT)- VLSI Devices?”; IEEE Transactions on Electron Devices; vol. ED-28; No. 11; Nov. 1981.
Nishizawa et al.; “Analysis of Static Characteristics of A Bipolar Mode Sit (BSIT)”; IEEE Transactions on Electron Devices; vol. ED-29; No. 11; Aug. 1982.
Caruso et al.; “Performance Analysis of A Bipolar Mode FET (BMFET) With Normally Off Characteristics”; IEEE Transactions on Power Electronics; vol. 3; No. 2; Apr. 1988.
Nishizawa et al.; “Fieldeffect Transistor Versus Analog Transistor (Static Induction Transistor)”; IEEE Transactions on Electron Devices; vol. ED-24; No. 4; Apr. 1975.

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