Method and structure for controlling the interface roughness...

Details Method and structure for controlling the interface roughness... Method and structure for controlling the interface roughness...

2002-06-28

2004-10-26

Flynn, Nathan J. (Department: 2826)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000, C438S656000

Reexamination Certificate

active

06809030

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor transistor manufacturing, and more particularly to a method for controlling the interface roughness of a low resistivity electrical contact, wherein a Co or Ni alloy is employed in forming the electrical contact.
BACKGROUND OF THE INVENTION
The low resistivity and the ease of formation have made cobalt disilicide a suitable choice as the contact material to the source, drain and gate of a transistor in ultra-large scale integration (ULSI). The main drawbacks of using cobalt disilicide over the more widely used titanium disilicide reside in an increase in junction leakage and a higher sensitivity to oxygen. It is an accepted principle that the increased junction leakage is caused by the roughness of the interface between the disilicide and the Si-containing substrate.
In the self-aligned silicide (salicide) process, a blanket TiN/Co film is deposited over the devices and annealed to form cobalt monosilicide over the exposed Si regions (source, drain and gate) of the transistor. A selective wet etch process is used to remove the TiN cap and any non-reacted cobalt left over in the oxide or nitride regions. The cobalt monosilicide is then further annealed to form cobalt disilicide.
The leakage observed during electrical testing is at least partially a consequence of disilicide spikes that extend into the silicon and through the junction. Since the silicide is formed by a reactive diffusion mechanism, roughening is expected at the formation of each of the silicide phases. Presently, it is not known which of the annealing stages contribute to the formation of the most damaging interface roughness. The first phase forms a metal rich Co
2
Si phase during which cobalt is the main diffusing element. This phase is followed closely in temperature by formation of the monosilicide (CoSi) during which silicon is the dominant diffusing species. At higher temperature, cobalt diffusion is mainly responsible for the formation of the disilicide (CoSi
2
).
SUMMARY OF THE INVENTION
Although not known, it is believed by the applicants of the present application that the area leakage problem described above originates from a non-uniform diffusion of Co into the silicon during formation of the silicide. This could occur during the formation of either the Co
2
Si phase or the CoSi
2
phase since these two phases are formed by diffusion of Co. In the formation of CoSi
2
, the grains in the preceding monosilicide are fairly uniform with an average grain size on the order of the film thickness. Considering that the distance between the spikes of CoSi
2
into Si is much larger than the film thickness, it is unlikely that a film with a uniform, small microstructure can lead to such a highly non-uniform diffusion. The formation of Co
2
Si, however, originates from the pure cobalt layer and the silicon single crystal. The cobalt layer can exhibit large variations in microstructure including different possible crystal structures.
Through extensive studies, applicants propose herein that the damaging interface roughness is a consequence of non-uniformities in the cobalt layer that develop in the first part of the anneal before silicidation. These non-uniformities are believed to be enhanced at each subsequent annealing step. In the present invention, applicants have determined that by controlling the Co microstructure, it is possible to tailor the properties of the interface between the silicon and the cobalt disilicide.
It is known that the hcp-phase (hexagonal close packed) of Co can show abnormal grain growth in which only the (002) grains expand laterally to a size many times larger than the film thickness while the other grains remain much smaller. A considerable stress reduction in the cobalt layer is observed during this abnormal grain growth which could be the driving force for the non-uniformities. Such large grains could be the source of spiking since it is easier for the cobalt to diffuse from triple junctions or grain boundaries. The grain growth can also be followed by a spatially non-uniform phase transformation of the cobalt from the hcp phase to the fcc (face centered cubic) phase. The simultaneous presence of the two Co phases at the beginning of the silicide formation could in itself lead to enhanced non-uniformity in the diffusion of Co. The fact that impurities in the film have different miscibility in these two Co phases could add to the non-uniformity by selectively hindering the diffusion of Co. The non-uniformity could arise from either precipitation of impurities during the Co transformation or impurities going into solution. For example, the formation of cobalt silicide is highly sensitive to oxygen and the solubility of the oxygen in the cobalt, although very small, is four times larger for the hcp phase as compared with the fcc phase.
The above problems are solved by utilizing the method of the present invention which comprises the steps of:
(a) forming an alloy layer having the formula MX over a silicon-containing substrate, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive;
(b) optionally forming an oxygen barrier layer over said alloy layer;
(c) annealing said alloy layer at a temperature which is effective in forming a MXSi layer; and
(d) removing said optional oxygen barrier layer and any remaining alloy layer.
In an optional embodiment of the present invention, a pre-annealing step is carried out between steps (a) and (c) or (b) and (c) at an annealing temperature which is sufficient to form a M
2
XSi layer in the structure. Typically, the pre-annealing step is carried out at a temperature that is lower than the temperature used in forming the MXSi layer.
It is noted that when a Co alloy is employed, a second annealing step follows the first annealing step described in (c) above to convert the CoXSi layer into a CoXSi
2
. Specifically, the second annealing step is carried out at a temperature that is greater than the temperature used to form the MXSi, i.e. monosilicide, layer.
It is noted that the terms M
2
XSi; MXSi and MXSi
2
are not used herein as empirical formulas. Rather the terms describe the following silicide phases:
M
2
XSi: metal rich alloy silicide phase.
MXSi: metal alloy monosilicide phase.
MXSi
2
: metal alloy disilicide phase.
Another aspect of the present invention relates to electrical contacts that are formed utilizing the method of the present invention. In accordance with one aspect of the present invention, an electrical contact to a region of a silicon-containing substrate is provided that comprises:
a substrate having an exposed region of a silicon-containing semiconductor material, said silicon-containing semiconductor material being doped with an impurity to provide carriers of holes, electrons or both holes and electrons; and
a first layer of CoXSi
2
(Co alloy disilicide phase) wherein X is an alloying additive, said alloying additive being present in said first layer in an amount of from about 0.01 to about 50 atomic %,
said first layer and said silicon-containing semiconductor material forming an interface having a predetermined roughness and being substantially free of Co silicide spikes descending into said silicon-containing semiconductor material.
In the case when Ni alloys are used in forming the electrical contact, the electrical contact comprises:
a substrate having an exposed region of a silicon-containing semiconductor material, said silicon-containing semiconductor material being doped with an impurity to provide carriers of holes, electrons or both holes and electrons; and
a first layer of NiXSi (Ni alloy monosilicide phase), wherein X is an alloying additive, said alloying additive being present in said first layer in an amount of from about 0.01 to about 50 atomic %,
said first layer and said silicon-containing semiconductor material forming an interface having a predetermined roughness and being substantially free of Ni silicide spikes descending into said silicon-containing semiconductor material.


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