Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-06-12
2004-07-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S154000, C438S155000, C438S618000, C438S622000, C257S306000, C257S347000, C257S348000, C257S350000, C257S352000
Reexamination Certificate
active
06759282
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention involves fabrication of semiconductor devices using Silicon-on-Insulator (SOI) technology. More specifically the invention is directed to the use of the SOI Buried Oxide (BOX) layer as an integral component of electronic devices and circuits.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology has emerged as an electronic fabrication technique that improves characteristics such as latchup and speed, although typically at higher manufacturing cost. The term SOI typically describes structures where devices are fabricated in single-crystal Si layers formed over an insulating film or substrate.
FIGS. 11A and 11B
show a typical conventional SOI structure, where a thin silicon device layer
110
formed on an insulator
111
is supported over substrate
112
. For current technology the substrate is most commonly silicon and the insulator is most commonly silicon dioxide. Devices
113
are formed in device layer
110
and interconnected by surface conductors
114
. The conventional SOI structure is predominantly created by one of two techniques.
The first process, known as SIMOX (Separation by IMplanted OXygen), consists of implantation of oxygen into an Si substrate at a prescribed depth and heating it to form a continuous layer of SiO
2
. The SIMOX process requires only a single wafer. The alternate process, shown in greater detail later, is commonly referred to as “Bonded SOI” and starts with two wafers, preferably with at least one having an oxide surface. The first wafer is the carrier wafer which is joined together with the second wafer, and the second wafer is “thinned” to leave a layer of silicon bonded onto the carrier wafer, separated by an insulator layer.
Both of the techniques have experienced many variations and enhancements over the years for improvement of yield and lower cost and to achieve desirable device layer quality for uniformity and defects. An important characteristic of conventional SOI that is obvious from
FIG. 11B
is that the insulator layer
111
is used primarily for isolating the silicon device layer
110
with its active devices
113
from the silicon substrate
112
. Thus, the conventional wisdom forms devices on the device layer
110
on only one side of the insulator layer
111
.
The problem with this approach is that, although devices and interconnects are formed similar to conventional substrates, SOI techniques introduce newer problems such as floating body effects. Additionally, conventional SOI structure takes up considerably more chip “real estate” than required in corresponding non-SOI structure, since floating body effects which not an issue with conventional substrates require additional connections to the channel regions. There are also added process steps to provide ground interconnections to the substrate. More important, the conventional approach fails to recognize that the insulator layer could provide more functionality than merely separating predetermined groups of devices from the substrate.
SUMMARY OF THE INVENTION
The inventors have recognized that the SOI insulator layer, or BOX (Buried OXide), can be an integral part of a specific device, and further, even circuits can be advantageously built around this innovative approach. That is to say, the BOX can be considered more than a mere passive isolation mechanism separating layers of devices. It can become an integral component even of an entire circuit. As will be demonstrated, by adopting this innovative approach, a whole new possibility opens up for SOI technology that provides improved device density and speed and fewer conductor interconnects between devices.
Therefore, an object of the invention is to teach methods in which the SOI insulator (BOX) is used as a building component at the device level.
Another object of the invention is to teach methods in which the BOX serves as a building component at the circuit level.
Another object of the present invention is to teach a method in which the BOX is used for functions other than simple isolation between layers of devices.
Another object of the present invention is to teach a method in which the BOX is even used for functions other than isolation even within a single device.
Another object of the present invention is to improve electronic device density on SOI chips.
Another object of the present invention is to reduce the number of conductor interconnects between devices on SOI chips.
Another object of the present invention is to reduce parasitics and increase speed on SOI chips.
Another object of the present invention is to teach methods for forming features in the substrate prior to the formation of SOI structure.
Another object of the present invention is to teach methods to form improved FET devices on SOI.
A still further object of the invention is demonstrate applications that take advantage of the above methods.
Yet another object of the invention is to demonstrate the above goals and techniques using established silicon manufacturing processes and equipment.
To achieve the above objects according to a first aspect of the invention, a method and structure is disclosed of fabricating an electronic device using an SOI technique resulting in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, where the first component and the second component are on opposite sides of the buried oxide layer so that the buried oxide layer performs a function within the electronic device.
According to a second aspect of the invention, a method is disclosed of fabricating an electronic circuit using an SOI technique, said SOI technique resulting in formation of at least one buried oxide layer, the electronic circuit comprising a plurality of interconnected electronic devices, each electronic device comprising a respective plurality of components. The method includes fabricating a predetermined first set of respective plurality of components to be on a first side of the buried oxide layer and fabricating a predetermined second set of respective plurality of components to be on a second side of the buried oxide layer, where the second side is the opposite side of the first side, and where the buried oxide layer performs a function integral to the functioning of at least one of the electronic devices.
According to a third aspect of the invention, a method is disclosed of SOI fabrication in which a buried oxide layer is formed, where the method includes forming a first set of device components to be on a first side of the buried oxide layer and forming a second set of device components to be on the side opposite the first side, where the buried oxide layer performs a function integral to the functioning of at least one device comprised of components from the first set of components and components from the second set of components.
According to a fourth aspect of the invention, a method and structure are disclosed of fabricating a DRAM cell using an an SOI technique on a substrate, where the SOI technique results in formation of at least one buried oxide layer. The method includes forming a buried capacitor beneath the buried oxide layer, subsequently forming an FET source and drain regions on top of the buried oxide layer, and interconnecting the capacitor to one of the source region or drain region with a via penetrating the buried oxide layer, where the via is a conductive material.
According to a fifth aspect of the invention, a method and structure are disclosed of fabricating a DRAM cell using an SOI technique, where the SOI technique results in formation of at least one buried oxide (BOX) layer, whereby a capacitor for the DRAM cell is formed by a process including forming a buried electrode in a substrate, wherein the buried electrode serves as a lower capacitor charge plate and forming a diffusion link between the diffusion region of a transistor located on the upper side of the BOX and a region to compr
Campbell John E.
Devine William T.
Srikrishnan Kris V.
Anya Igwe U.
Gibb Fred
International Business Machines - Corporation
McGinn & Gibb
Pepper Margaret A.
LandOfFree
Method and structure for buried circuits and devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for buried circuits and devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for buried circuits and devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3254282