Method and/or apparatus for performing static timing...

Details Method and/or apparatus for performing static timing... Method and/or apparatus for performing static timing...

2007-06-12

2007-06-12

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

10789883

ABSTRACT:
An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.

REFERENCES:
patent: 5459736 (1995-10-01), Nakamura
patent: 5471481 (1995-11-01), Okumoto et al.
patent: 5487074 (1996-01-01), Sullivan
patent: 5878055 (1999-03-01), Allen

Affiliated with

Also associated with

Rating

Method and/or apparatus for performing static timing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and/or apparatus for performing static timing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and/or apparatus for performing static timing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3863575