Method and module for universal test of communication ports

Details Method and module for universal test of communication ports Method and module for universal test of communication ports

2007-01-23

2007-01-23

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S735000, C714S820000

Reexamination Certificate

active

09262960

ABSTRACT:
The present invention relates to a method and an universal module for testing functions of communication ports of a computer, including both parallel port and serial port. The module includes a logic control unit and connects to a communication port (a serial or a parallel port) for testing the open or short conditions of the ports through walk 1′ and a walk 0′ logic tests. The testing module not only can check the open condition of a parallel port, but also can check the open and short conditions of a parallel port and a serial port.

REFERENCES:
patent: 5557741 (1996-09-01), Jones
patent: 5819112 (1998-10-01), Kusters
patent: 5875293 (1999-02-01), Bell et al.
patent: 6374372 (2002-04-01), Ha

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