Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-13
2002-09-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000
Reexamination Certificate
active
06444518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a device separation film in a semiconductor device. More particularly, the disclosed method relates to a method of manufacturing a device separation film in a semiconductor device by which a silicon growth layer is formed in order to reduce the aspect ratio of a trench, in a manner that the trench is filled so that voids are not generated.
2. Description of the Prior Art
In STI (shallow trench isolation) structures, device separation films are applied to devices below 0.10 &mgr;m. The most significant problem associated with such device separation films is gap fill. It is nearly impossible to provide a device separation film without voids using presently available gap fill materials.
Therefore, a modified STI structure using a SEG (selective epitaxial growth) structure has been introduced as a new type of a device separation film structure. In this structure, silicon is grown at the bottom of a trench by a SEG method in order to lower an otherwise high aspect ratio in a device below 0.01 &mgr;m. However, a thermal oxide film is formed in order to secure an interfacial characteristic between the silicon of the etched trench and a silicon growth layer or between the silicon of the trench and a gap fill material. In order to form silicon at the bottom of the trench by SEG method, however, the thermal oxide film at the bottom of the trench must be removed. The process of removing the thermal oxide film from the bottom of the trench must keep the oxide film at the side of the trench intact.
FIG. 1A
is a TEM photograph showing a cross-sectional view of a device separation film manufactured by a conventional method and
FIG. 1B
is an enlarged view thereof. A trench is formed in a silicon substrate
1
and a thermal oxide film
5
is formed at the sidewall of the trench. At the bottom of the trench, some of the thermal oxide film
5
a
remains which prevents normal silicon growth, and, as a result, an abnormal silicon growth layer
6
is formed. Therefore, there is a need for a process where the thermal oxide film at the bottom of the trench is removed while leaving the thermal oxide film at the sides of the trench intact.
SUMMARY OF THE DISCLOSURE
The disclosed method teaches a method of manufacturing a device separation film in a semiconductor device capable of forming a device separation film without voids, by completely removing a thermal oxide film at the bottom of a trench while minimizing loss of the thermal oxide film at the sidewall of the trench, so that silicon can be normally grown to reduce the aspect ratio.
A method of manufacturing a device separation film in a semiconductor device is disclosed which is characterized in that it comprises the steps of providing a silicon substrate in which a trench is formed; performing a plasma process for the surface of the trench; forming a thermal oxide film in the trench; removing the thermal oxide film at the bottom of the trench; cleaning the silicon surface at the bottom of the trench and then forming a silicon growth layer by SEG process; and filling an insulating material into the trench and then performing a chemical mechanical polishing process.
In the above step, the plasma process employs fluorine-based such as NF
3
, CF
4
etc. or chlorine-based such as Cl
2
, CCl
4
etc. and O
2
, which are mixed at the rate of 3:1 to 5:1.
The thermal oxide film is formed by dry oxidization process using O
2
or wet oxidization process using H
2
/O
2
at a temperature ranging from about 700° C. to about 1100° C. The thermal oxide film is formed in thickness ranging from about 100 Å to about 140 Å. The thermal oxide film at the bottom of the trench is removed by dry etching or wet etching.
The silicon surface cleaning process is performed in two steps, wherein a first process is performed under the conditions of a temperature ranging from about 100° C. to about 130° C. and the ratio of H
2
SO
4
and H
2
O
2
ranging from about 3:1 to about 500:1 for a time period ranging from about 3 minutes to about 10 minutes, and a second process is performed under the conditions of a temperature ranging from about 50° C. to about 100° and a pure water or a ratio of H
2
O to HF ranging from about 50:1 to about 500:1. The silicon surface cleaning process employs a rapid thermal process (RTP), in case that it is performed in-situ when the SEG process is performed. The silicon surface cleaning process is, when the SEG process is performed in the UHV-CVD equipment, in-situ performed under vacuum atmosphere at a temperature ranging from about 700° C. to about 750° C. and at a pressure ranging from about 0.01 Torr to about 10 Torr for a time period ranging from about 10 seconds to about 200 seconds.
The SEG process is performed by CVD method using MS/H
2
/HCl gas or DCS/H
2
/HCl gas.
The SEG process is performed under the conditions of a temperature ranging from about 750° C. to about 850° C. and a pressure ranging from about 5 Torr to about 100 Torr, using a DCS flow rate ranging from about 0.1 sccm to about 1 sccm, a H
2
flow rate ranging from about 30 sccm to about 150 sccm and a HCl flow rate ranging from about 0 sccm to about 1 sccm. The SEG process is performed under the conditions of a temperature ranging from about 750° C. to about 850° C. and a pressure ranging from about 5 Torr to about 100 Torr, using a MS flow rate ranging from about 0.1 sccm to about 1 sccm, a H
2
flow rate ranging from about 30 sccm to about 150 sccm and a HCl flow rate ranging from about 0.5 sccm to about 5 sccm, when a MS-H
2
—HCl system is applied. The SEG process, when it is performed in the UHV-CVD equipment, is performed under the conditions of a temperature ranging from about 600° C. to about 750° C. and a pressure ranging from about 1 Torr to about 50 m Torr using a Si
2
H
6
flow rate ranging from about 1 sccm to about 20 sccm, a H
2
flow rate ranging from about 0 sccm to about 100 sccm and a HCl flow rate ranging from about 0.01 sccm to about 5 sccm.
REFERENCES:
patent: 5869359 (1999-02-01), Prahakar
patent: 5950106 (1999-09-01), May et al.
patent: 5994200 (1999-11-01), Kim
patent: 6020230 (2000-02-01), Wu
patent: 6124211 (2000-09-01), Butterbaugh et al.
patent: 6177332 (2001-01-01), Chen et al.
patent: 6303512 (2001-10-01), Laermer et al.
Jang Min Sik
Ki Young Jong
Hyundai Electronics Industries Co,. Ltd.
Le Bau T
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