Method and latch circuit for implementing enhanced...

Details Method and latch circuit for implementing enhanced... Method and latch circuit for implementing enhanced...

2006-09-05

2006-09-05

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07103857

ABSTRACT:
A method and latch circuit for implementing enhanced performance includes critical data and clock paths and non-critical sections. A low voltage threshold (LVT) transistor is used only in the critical data and clock paths. The non-critical sections are implemented with regular VT, (RVT), or low leakage (LLD) transistors. The latch circuit advantageously is implemented using LVT devices in the internal critical paths of the latch and RVT output buffer transistors.

REFERENCES:
patent: 5629638 (1997-05-01), Kumar
patent: 5774367 (1998-06-01), Reyes et al.
patent: 5982211 (1999-11-01), Ko
patent: 6090153 (2000-07-01), Chen et al.
patent: 6794914 (2004-09-01), Sani et al.

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