Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-28
2000-10-31
Elms, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, 438396, 438246, H01L 218242
Patent
active
061401765
ABSTRACT:
A method of fabricating a self-aligned node contact window starts by forming a bit line on a substrate having a transistor, in which the transistor includes a first source/drain region and a second source/drain region. The bit line is coupled electrically with the first source/drain region of the transistor and there is a cap layer and a first conductive layer formed on the bit line. An insulating layer that is conformal with the bit line, the cap layer and the first conductive layer is formed to serve as an etching stop layer for subsequently forming a conductive spacer. A conductive spacer is formed on the insulating layer of the sidewall of the bit line, the cap layer and the first conductive layer. Using the first conductive layer and the conductive spacer as a mask, an etching process is performed to form a self-aligned node contact window and the second source/drain is thus exposed.
REFERENCES:
patent: 5422315 (1995-06-01), Kobayashi
patent: 5466637 (1995-11-01), Kim
patent: 5946568 (1999-08-01), Hsiao et al.
Elms Richard
Luu Pho
United Microelectronics Corp.
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