Method and equipment for automatically testing electronic compon

Details Method and equipment for automatically testing electronic compon Method and equipment for automatically testing electronic compon

1997-05-14

1999-12-21

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060063467

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to methods and equipment for automatically testing electronic components containing sequential digital portions, and more particularly to test equipment which makes it possible to test a plurality of such components in parallel.


BACKGROUND INFORMATION

Most digital circuits on the market are tested by their manufacturers several times before they are delivered. Component testers are assigned to generate digital signals (logic "0" or "1" states) and to verify the presence of transitions at the output of the circuit under test. The signals generated and the comparison signals are programmable both in time and in level. A component tester must generate and/or compare signals on all of the function pins of the component under test simultaneously.
Defining the signals to be generated and/or to be compared is generally extremely complex. Testing a microprocessor can give rise to strings of several million zeros and ones in the same sequence. To define such signals, the notion of period is used to define a time slice within which a more simple signal is described. Such a signal is subdivided into an item of time information (also referred to as a "time marker") and an event (e.g. a transition or a test).
Executing a functional test thus results in a memory running in which each line corresponds to a period and whose content represents the time information and the events defining the signal within the period for each pin. In addition to the time information and the events, there is an instruction serving to manage the running of the memory. The instruction is common to all of the function pins of the circuit under test. The most commonly used instruction is the instruction consisting in going to read the following line (INC instruction). This memory is referred to as the "main" memory. "Sub-program" memories are also used.
This architecture, based on running the memories, is deterministic, i.e. the architecture assumes that it is possible, a priori, to know exactly what is going to happen at a given instant on the output pins of the circuit under test.
Digital components (e.g. microprocessors) exist in which the internal logic state cannot be known a priori. Therefore, the test signals cannot be known a priori. To test this type of component, it must be possible to bring the component into a known state. For this purpose, it must be possible to generate signals (e.g. clock signals) until a predetermined event or succession of events appears on one or more outputs of the circuit under test. To manage the running of the main memory or of the sub-program memory under such conditions, suitable instructions exist that consist in looping the memory so long as a particular condition has not occurred. The method which consists of waiting for a circuit to put itself in a predetermined state is called "matching". The simplest example is to consider a divider whose initial state is not known. Clock signals generated at the input of the divider cause a transition to occur once every n clock edges. To synchronize this type of component, it is necessary to generate clock signals until an output transition appears. Once such a transition appears, the divider is in a known state, and the remainder of the test is performed in deterministic manner. If the component under test is bad, the exit condition from the matching sequence might never be found. A maximum number of loops must be initially programmed to avoid looping indefinitely. For example, for a divider by n, the output transition must be found in less than n+1 clock edges. In which case, after n+1 edges, the matching sequence stops and the divider is deemed to be bad. In certain complex cases, the time necessary for deeming a matching sequence to be bad can be quite long.
The architecture of a tester contains a portion for generating/receiving digital signals and a portion for shaping said signals. Usually, the shaping portion constitutes the measurement head whereas the generate/receive portion can be situated in a s

REFERENCES:
patent: 5025205 (1991-06-01), Mydill et al.
Douglas Mirizzi et al, "Implementation of Parallelsite Test on an 8-Bit Configurable Microcontroller", Proceedings International Test Conference, pp. 227-235, Jan. 1993.
"How Genrad's New Tester Copes with VHSIC Chips", Electronics, vol. 59, May 1986, New York US, pp. 49-52.
Kiyosato, "Testing Method of Large Scale Integrated Circuit", Patent Abstracts of Japan, vol. 007, No. 241, p. 232, Oct. 1983.
Kiyosato, "LSI Tester", Patent Abstracts of Japan, vol. 008, No. 129, p. 280, Jun. 1984.

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