Method and dual interlocked storage cell latch for...

Details Method and dual interlocked storage cell latch for... Method and dual interlocked storage cell latch for...

2007-10-10

2010-02-09

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C327S199000, C327S202000, C326S010000, C326S012000

Reexamination Certificate

active

07661047

ABSTRACT:
A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode.

REFERENCES:
patent: 6127864 (2000-10-01), Mavis et al.
patent: 7095262 (2006-08-01), Petersen et al.
patent: 7215581 (2007-05-01), Lotz et al.
patent: 2008/0180153 (2008-07-01), Sachdev et al.
patent: 2008/0222468 (2008-09-01), Rickert et al.

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