Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2008-03-18
2008-03-18
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S462000
Reexamination Certificate
active
07344956
ABSTRACT:
A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member. The one or more bonding pads and the antistiction region are exposed while the one or more deflection devices is maintained within the portion of the cavity region.
REFERENCES:
patent: 3997964 (1976-12-01), Holbrook et al.
patent: 4094058 (1978-06-01), Yasutake et al.
patent: 5457022 (1995-10-01), Hioki et al.
patent: 5801068 (1998-09-01), Sooriakumar et al.
patent: 6075280 (2000-06-01), Yung et al.
patent: 6093623 (2000-07-01), Forbes
patent: 6294439 (2001-09-01), Sasaki et al.
patent: 6344369 (2002-02-01), Huang et al.
patent: 6396711 (2002-05-01), Degani et al.
patent: 6417075 (2002-07-01), Haberger et al.
patent: 6514789 (2003-02-01), Denton et al.
patent: 6562658 (2003-05-01), Ohuchi et al.
patent: 6566745 (2003-05-01), Byenne
patent: 6653210 (2003-11-01), Choo et al.
patent: 6664503 (2003-12-01), Hsieh et al.
patent: 6822326 (2004-11-01), Enquist et al.
patent: 6891592 (2005-05-01), Magana et al.
patent: 6939473 (2005-09-01), Nasiri et al.
patent: 7005732 (2006-02-01), Horning et al.
patent: 2001/0022382 (2001-09-01), Shook
patent: 2002/0163069 (2002-11-01), Lu et al.
patent: 2002/0181838 (2002-12-01), Cunningham et al.
patent: 2003/0025984 (2003-02-01), Gudeman et al.
patent: 2004/0087053 (2004-05-01), Lytle et al.
patent: 2004/0219764 (2004-11-01), Syllaios et al.
patent: 2005/0233546 (2005-10-01), Oohata et al.
patent: 2006/0046436 (2006-03-01), Ohuchi et al.
patent: 2006/0138673 (2006-06-01), Kim
patent: 2006/0160273 (2006-07-01), Chen
patent: WO 01/29890 (2001-04-01), None
patent: WO 03/054927 (2003-07-01), None
patent: WO 2004/099065 (2004-11-01), None
Chen Dongmin
Chen Philip
Yang Xiao “Charles”
Coleman W. David
Miradia Inc.
Nguyen Khiem D
Townsend and Townsend / and Crew LLP
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