Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2006-07-04
2006-07-04
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Precharge
C365S201000, C365S230060
Reexamination Certificate
active
07072234
ABSTRACT:
A semiconductor memory is provided which is operable in at least a test mode. Such semiconductor memory includes a memory array, the memory array including a plurality of memory cells which are accessible through a plurality of respective wordlines and a plurality of respective bitlines. A row decoder driver is operable to activate one wordline of the plurality of wordlines at a first point in time that is determined in relation to a first signal and to deactivate the wordline at a second point in time that is determined in relation to a second signal. The semiconductor memory further includes a precharge circuit which is operable to precharge the bitline at a third point in time, the third point in time occurring no sooner than the second point in time. A variable length delay circuit is operable to output the second signal at a delayed timing after the first signal and delayed in relation to the first signal, the delayed timing having a controllably variable length.
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Infineon - Technologies AG
Slater & Matsil, L.L.P
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