Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-12-15
2010-02-16
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C711S168000
Reexamination Certificate
active
07665003
ABSTRACT:
A method of testing a memory is provided that includes initiating a test on a computer readable memory. The computer readable memory provides output data associated with the test. Further, the method includes selecting to receive the output data from a first register or a second register. In a particular embodiment, the method may include selecting to receive the output data from the first register or the second register by use of a control line. In another particular embodiment, the method may include selecting to receive the RAM input data from the first register or the second register by use of a control line. The control line is configured dynamically by hardware or software on cycle by cycle basis. In a particular embodiment, the test is a built-in-self-test (BIST).
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Bassett Paul
Shen Jian
Ellis Kevin L
Kamarchik Peter M.
Nguyen Steve
Pauley Nicholas J.
QUALCOMM Incorporated
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